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net: mscc: Enable all ports in QSGMII
When Ocelot phy-mode is QSGMII, all 4 ports involved in
QSGMII shall be kept out of reset and
Tx lanes shall be enabled to pass the data.
Fixes: a556c76adc
("net: mscc: Add initial Ocelot switch support")
Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
Signed-off-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Co-developed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
46b1c18f9d
commit
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@ -267,6 +267,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
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struct phy *serdes;
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void __iomem *regs;
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char res_name[8];
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int phy_mode;
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u32 port;
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if (of_property_read_u32(portnp, "reg", &port))
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@ -292,11 +293,11 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
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if (err)
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return err;
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err = of_get_phy_mode(portnp);
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if (err < 0)
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phy_mode = of_get_phy_mode(portnp);
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if (phy_mode < 0)
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ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA;
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else
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ocelot->ports[port]->phy_mode = err;
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ocelot->ports[port]->phy_mode = phy_mode;
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switch (ocelot->ports[port]->phy_mode) {
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case PHY_INTERFACE_MODE_NA:
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@ -304,6 +305,13 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
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case PHY_INTERFACE_MODE_SGMII:
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break;
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case PHY_INTERFACE_MODE_QSGMII:
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/* Ensure clock signals and speed is set on all
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* QSGMII links
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*/
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ocelot_port_writel(ocelot->ports[port],
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DEV_CLOCK_CFG_LINK_SPEED
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(OCELOT_SPEED_1000),
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DEV_CLOCK_CFG);
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break;
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default:
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dev_err(ocelot->dev,
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