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clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flag
Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state, being a divider value of zero. Some hardware implementations allow a zero divider which simply doesn't alter the frequency. I.e. it acts like a divide by one or bypassing the divider. This flag is used to handle such HW in the clk-divider model. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -109,8 +109,9 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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div = _get_div(divider, val);
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div = _get_div(divider, val);
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if (!div) {
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if (!div) {
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WARN(1, "%s: Invalid divisor for clock %s\n", __func__,
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WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
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__clk_get_name(hw->clk));
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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__clk_get_name(hw->clk));
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return parent_rate;
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return parent_rate;
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}
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}
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@ -249,9 +249,14 @@ struct clk_div_table {
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* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
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* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
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* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
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* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
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* the raw value read from the register, with the value of zero considered
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* the raw value read from the register, with the value of zero considered
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* invalid
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* invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
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* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
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* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
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* the hardware register
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* the hardware register
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* CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
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* CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
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* Some hardware implementations gracefully handle this case and allow a
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* zero divisor by not modifying their input clock
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* (divide by one / bypass).
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*/
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*/
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struct clk_divider {
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struct clk_divider {
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struct clk_hw hw;
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struct clk_hw hw;
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@ -265,6 +270,7 @@ struct clk_divider {
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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extern const struct clk_ops clk_divider_ops;
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extern const struct clk_ops clk_divider_ops;
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struct clk *clk_register_divider(struct device *dev, const char *name,
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struct clk *clk_register_divider(struct device *dev, const char *name,
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