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https://github.com/torvalds/linux
synced 2024-11-05 18:23:50 +00:00
clk: tegra: move some PLLC and PLLXC init to clk-pll.c
VCO min clipping, dynamic ramp setup and IDDQ init can be done in the respective PLL clk_register functions if the parent is already registered. This is done for other some PLLs already. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This commit is contained in:
parent
5bb9d26700
commit
04edb099a4
2 changed files with 110 additions and 92 deletions
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@ -773,6 +773,48 @@ static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
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return 1;
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}
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static unsigned long _clip_vco_min(unsigned long vco_min,
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unsigned long parent_rate)
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{
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return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
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}
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static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
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void __iomem *clk_base,
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unsigned long parent_rate)
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{
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u32 val;
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u32 step_a, step_b;
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switch (parent_rate) {
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case 12000000:
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case 13000000:
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case 26000000:
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step_a = 0x2B;
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step_b = 0x0B;
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break;
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case 16800000:
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step_a = 0x1A;
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step_b = 0x09;
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break;
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case 19200000:
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step_a = 0x12;
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step_b = 0x08;
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break;
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default:
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pr_err("%s: Unexpected reference rate %lu\n",
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__func__, parent_rate);
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WARN_ON(1);
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return -EINVAL;
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}
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val = step_a << pll_params->stepa_shift;
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val |= step_b << pll_params->stepb_shift;
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writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
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return 0;
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}
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static int clk_pll_iddq_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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@ -1423,11 +1465,39 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
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spinlock_t *lock)
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{
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struct tegra_clk_pll *pll;
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struct clk *clk;
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struct clk *clk, *parent;
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unsigned long parent_rate;
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int err;
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u32 val, val_iddq;
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parent = __clk_lookup(parent_name);
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if (IS_ERR(parent)) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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return ERR_PTR(-EINVAL);
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}
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if (!pll_params->pdiv_tohw)
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return ERR_PTR(-EINVAL);
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parent_rate = __clk_get_rate(parent);
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pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
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err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
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if (err)
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return ERR_PTR(err);
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val = readl_relaxed(clk_base + pll_params->base_reg);
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val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
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if (val & PLL_BASE_ENABLE)
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WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
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else {
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val_iddq |= BIT(pll_params->iddq_bit_idx);
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writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
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}
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pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
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pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
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freq_table, lock);
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@ -1455,6 +1525,9 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
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struct clk *clk;
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pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
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pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
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pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
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freq_table, lock);
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if (IS_ERR(pll))
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@ -1498,11 +1571,23 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
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spinlock_t *lock)
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{
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struct tegra_clk_pll *pll;
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struct clk *clk;
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struct clk *clk, *parent;
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unsigned long parent_rate;
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if (!pll_params->pdiv_tohw)
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return ERR_PTR(-EINVAL);
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parent = __clk_lookup(parent_name);
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if (IS_ERR(parent)) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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return ERR_PTR(-EINVAL);
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}
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parent_rate = __clk_get_rate(parent);
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pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
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pll_flags |= TEGRA_PLL_BYPASS;
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pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
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pll_flags |= TEGRA_PLLM;
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@ -1543,14 +1628,16 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
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return ERR_PTR(-EINVAL);
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}
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parent_rate = __clk_get_rate(parent);
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pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
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pll_flags |= TEGRA_PLL_BYPASS;
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pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
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freq_table, lock);
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if (IS_ERR(pll))
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return ERR_CAST(pll);
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parent_rate = __clk_get_rate(parent);
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/*
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* Most of PLLC register fields are shadowed, and can not be read
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* directly from PLL h/w. Hence, actual PLLC boot state is unknown.
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@ -1077,63 +1077,6 @@ static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
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writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
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}
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static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
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{
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pll_params->vco_min =
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DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
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}
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static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
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void __iomem *clk_base)
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{
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u32 val;
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u32 step_a, step_b;
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switch (pll_ref_freq) {
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case 12000000:
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case 13000000:
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case 26000000:
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step_a = 0x2B;
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step_b = 0x0B;
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break;
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case 16800000:
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step_a = 0x1A;
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step_b = 0x09;
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break;
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case 19200000:
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step_a = 0x12;
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step_b = 0x08;
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break;
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default:
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pr_err("%s: Unexpected reference rate %lu\n",
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__func__, pll_ref_freq);
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WARN_ON(1);
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return -EINVAL;
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}
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val = step_a << pll_params->stepa_shift;
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val |= step_b << pll_params->stepb_shift;
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writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
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return 0;
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}
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static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
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void __iomem *clk_base)
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{
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u32 val, val_iddq;
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val = readl_relaxed(clk_base + pll_params->base_reg);
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val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
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if (val & BIT(30))
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WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
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else {
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val_iddq |= BIT(pll_params->iddq_bit_idx);
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writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
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}
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}
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static void __init tegra114_pll_init(void __iomem *clk_base,
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void __iomem *pmc)
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{
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@ -1141,28 +1084,23 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
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struct clk *clk;
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/* PLLC */
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_clip_vco_min(&pll_c_params);
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if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) {
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_init_iddq(&pll_c_params, clk_base);
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clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
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pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
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pll_c_freq_table, NULL);
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clk_register_clkdev(clk, "pll_c", NULL);
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clks[TEGRA114_CLK_PLL_C] = clk;
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clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
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pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
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pll_c_freq_table, NULL);
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clk_register_clkdev(clk, "pll_c", NULL);
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clks[TEGRA114_CLK_PLL_C] = clk;
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/* PLLC_OUT1 */
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clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
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clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
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8, 8, 1, NULL);
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clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
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clk_base + PLLC_OUT, 1, 0,
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CLK_SET_RATE_PARENT, 0, NULL);
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clk_register_clkdev(clk, "pll_c_out1", NULL);
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clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
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}
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/* PLLC_OUT1 */
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clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
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clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
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8, 8, 1, NULL);
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clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
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clk_base + PLLC_OUT, 1, 0,
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CLK_SET_RATE_PARENT, 0, NULL);
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clk_register_clkdev(clk, "pll_c_out1", NULL);
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clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
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/* PLLC2 */
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_clip_vco_min(&pll_c2_params);
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clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0,
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&pll_c2_params, TEGRA_PLL_USE_LOCK,
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pll_cx_freq_table, NULL);
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@ -1170,7 +1108,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
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clks[TEGRA114_CLK_PLL_C2] = clk;
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/* PLLC3 */
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_clip_vco_min(&pll_c3_params);
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clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0,
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&pll_c3_params, TEGRA_PLL_USE_LOCK,
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pll_cx_freq_table, NULL);
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@ -1232,7 +1169,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
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clks[TEGRA114_CLK_PLL_P_OUT4] = clk;
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/* PLLM */
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_clip_vco_min(&pll_m_params);
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clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
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&pll_m_params, TEGRA_PLL_USE_LOCK,
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@ -1255,15 +1191,11 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
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CLK_SET_RATE_PARENT, 1, 1);
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/* PLLX */
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_clip_vco_min(&pll_x_params);
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if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
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_init_iddq(&pll_x_params, clk_base);
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clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
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pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
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TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
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clk_register_clkdev(clk, "pll_x", NULL);
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clks[TEGRA114_CLK_PLL_X] = clk;
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}
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clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
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pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
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TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
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clk_register_clkdev(clk, "pll_x", NULL);
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clks[TEGRA114_CLK_PLL_X] = clk;
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/* PLLX_OUT0 */
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clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
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@ -1356,7 +1288,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
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clks[TEGRA114_CLK_PLL_A_OUT0] = clk;
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/* PLLRE */
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_clip_vco_min(&pll_re_vco_params);
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clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
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0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK,
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NULL, &pll_re_lock, pll_ref_freq);
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