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ath9k: Fix bug in calibration initialization
This patch fixes a bug in ath9k_hw_init_cal() where the wrong calibration was being done for non-AR9285 chipsets. Also add a few helpful comments. Cc: stable@kernel.org Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -918,34 +918,15 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
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return true;
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return true;
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}
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}
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bool ath9k_hw_init_cal(struct ath_hw *ah,
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bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
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struct ath9k_channel *chan)
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{
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{
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if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
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if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
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if (!ar9285_clc(ah, chan))
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if (!ar9285_clc(ah, chan))
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return false;
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return false;
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} else if (AR_SREV_9280_10_OR_LATER(ah)) {
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} else {
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if (AR_SREV_9280_10_OR_LATER(ah)) {
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REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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/* Kick off the cal */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_CAL, 0,
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AH_WAIT_TIMEOUT)) {
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"offset calibration failed to complete in 1ms; "
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"noisy environment?\n");
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return false;
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}
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REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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}
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}
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/* Calibrate the AGC */
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/* Calibrate the AGC */
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@ -953,6 +934,7 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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AR_PHY_AGC_CONTROL_CAL);
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/* Poll for offset calibration complete */
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
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0, AH_WAIT_TIMEOUT)) {
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0, AH_WAIT_TIMEOUT)) {
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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@ -965,18 +947,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
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REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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}
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}
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}
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/* Do PA Calibration */
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/* Do PA Calibration */
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if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
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if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
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ath9k_hw_9285_pa_cal(ah);
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ath9k_hw_9285_pa_cal(ah);
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/* Do NF Calibration */
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/* Do NF Calibration after DC offset and other calibrations */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
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AR_PHY_AGC_CONTROL_NF);
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ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
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ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
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/* Enable IQ, ADC Gain and ADC DC offset CALs */
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if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
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if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
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if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
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if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
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INIT_CAL(&ah->adcgain_caldata);
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INIT_CAL(&ah->adcgain_caldata);
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