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Merge branches 'clk-microchip', 'clk-samsung' and 'clk-qcom' into clk-next

Browse source 
* clk-microchip:
  clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
  clock, reset: microchip: move all mpfs reset code to the reset subsystem

* clk-samsung:
  clk: samsung: Don't register clkdev lookup for the fixed rate clocks
  clk: samsung: gs101: drop unused HSI2 clock parent data
  clk: samsung: gs101: mark some apm UASC and XIU clocks critical
  clk: samsung: gs101: add support for cmu_hsi2
  clk: samsung: gs101: add support for cmu_hsi0
  dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
  dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
  clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
  clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
  clk: samsung: exynosautov9: fix wrong pll clock id value
  dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema
  clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
  clk: samsung: Implement manual PLL control for ARM64 SoCs

* clk-qcom: (27 commits)
  clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
  clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
  clk: qcom: Fix SM_GPUCC_8650 dependencies
  clk: qcom: Fix SC_CAMCC_8280XP dependencies
  clk: qcom: mmcc-msm8998: fix venus clock issue
  clk: qcom: dispcc-sm8650: fix DisplayPort clocks
  clk: qcom: dispcc-sm8550: fix DisplayPort clocks
  clk: qcom: dispcc-sm6350: fix DisplayPort clocks
  clk: qcom: dispcc-sm8450: fix DisplayPort clocks
  clk: qcom: clk-cbf-8996: use HUAYRA_APSS register map for cbf_pll
  clk: qcom: apss-ipq-pll: constify clk_init_data structures
  clk: qcom: apss-ipq-pll: constify match data structures
  clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'
  clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs'
  clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
  clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
  clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
  clk: qcom: clk-rcg: introduce support for multiple conf for same freq
  clk: qcom: hfpll: Add QCS404-specific compatible
  dt-bindings: clock: qcom,hfpll: Convert to YAML
  ...
This commit is contained in:
Stephen Boyd 2024-05-16 18:09:14 -07:00
parent 4a35e6fc41 bc2da26599 0dc83ad8bf e2211387ed
commit 03be434863
35 changed files with 2348 additions and 609 deletions
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55
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
View file

@ -30,16 +30,18 @@ properties:
- google,gs101-cmu-top
- google,gs101-cmu-apm
- google,gs101-cmu-misc
- google,gs101-cmu-hsi0
- google,gs101-cmu-hsi2
- google,gs101-cmu-peric0
- google,gs101-cmu-peric1
clocks:
minItems: 1
maxItems: 3
maxItems: 5
clock-names:
minItems: 1
maxItems: 3
maxItems: 5
"#clock-cells":
const: 1
@ -72,6 +74,55 @@ allOf:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: google,gs101-cmu-hsi0
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- description: HSI0 bus clock (from CMU_TOP)
- description: DPGTC (from CMU_TOP)
- description: USB DRD controller clock (from CMU_TOP)
- description: USB Display Port debug clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: dpgtc
- const: usb31drd
- const: usbdpdbg
- if:
properties:
compatible:
contains:
enum:
- google,gs101-cmu-hsi2
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- description: High Speed Interface bus clock (from CMU_TOP)
- description: High Speed Interface pcie clock (from CMU_TOP)
- description: High Speed Interface ufs clock (from CMU_TOP)
- description: High Speed Interface mmc clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: pcie
- const: ufs
- const: mmc
- if:
properties:
compatible:

63
Documentation/devicetree/bindings/clock/qcom,hfpll.txt
View file

@ -1,63 +0,0 @@
High-Frequency PLL (HFPLL)
PROPERTIES
- compatible:
Usage: required
Value type: <string>:
shall contain only one of the following. The generic
compatible "qcom,hfpll" should be also included.
"qcom,hfpll-ipq8064", "qcom,hfpll"
"qcom,hfpll-apq8064", "qcom,hfpll"
"qcom,hfpll-msm8974", "qcom,hfpll"
"qcom,hfpll-msm8960", "qcom,hfpll"
"qcom,msm8976-hfpll-a53", "qcom,hfpll"
"qcom,msm8976-hfpll-a72", "qcom,hfpll"
"qcom,msm8976-hfpll-cci", "qcom,hfpll"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: address and size of HPLL registers. An optional second
element specifies the address and size of the alias
register region.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the xo clock.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "xo".
- clock-output-names:
Usage: required
Value type: <string>
Definition: Name of the PLL. Typically hfpllX where X is a CPU number
starting at 0. Otherwise hfpll_Y where Y is more specific
such as "l2".
Example:
1) An HFPLL for the L2 cache.
clock-controller@f9016000 {
compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
reg = <0xf9016000 0x30>;
clocks = <&xo_board>;
clock-names = "xo";
clock-output-names = "hfpll_l2";
};
2) An HFPLL for CPU0. This HFPLL has the alias register region.
clock-controller@f908a000 {
compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
clocks = <&xo_board>;
clock-names = "xo";
clock-output-names = "hfpll0";
};

69
Documentation/devicetree/bindings/clock/qcom,hfpll.yaml Normal file
View file

@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm High-Frequency PLL
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description:
The HFPLL is used as CPU PLL on various Qualcomm SoCs.
properties:
compatible:
oneOf:
- enum:
- qcom,msm8974-hfpll
- qcom,msm8976-hfpll-a53
- qcom,msm8976-hfpll-a72
- qcom,msm8976-hfpll-cci
- qcom,qcs404-hfpll
- const: qcom,hfpll
deprecated: true
reg:
items:
- description: HFPLL registers
- description: Alias register region
minItems: 1
'#clock-cells':
const: 0
clocks:
items:
- description: board XO clock
clock-names:
items:
- const: xo
clock-output-names:
description:
Name of the PLL. Typically hfpllX where X is a CPU number starting at 0.
Otherwise hfpll_Y where Y is more specific such as "l2".
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
- clock-output-names
additionalProperties: false
examples:
- |
clock-controller@f908a000 {
compatible = "qcom,msm8974-hfpll";
reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
#clock-cells = <0>;
clock-output-names = "hfpll0";
clocks = <&xo_board>;
clock-names = "xo";
};

57
Documentation/devicetree/bindings/clock/samsung,s3c6400-clock.yaml Normal file
View file

@ -0,0 +1,57 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,s3c6400-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C6400 SoC clock controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names and/or provided as clock inputs to this clock controller:
- "fin_pll" - PLL input clock (xtal/extclk) - required,
- "xusbxti" - USB xtal - required,
- "iiscdclk0" - I2S0 codec clock - optional,
- "iiscdclk1" - I2S1 codec clock - optional,
- "iiscdclk2" - I2S2 codec clock - optional,
- "pcmcdclk0" - PCM0 codec clock - optional,
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/samsung,s3c64xx-clock.h header.
properties:
compatible:
enum:
- samsung,s3c6400-clock
- samsung,s3c6410-clock
reg:
maxItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller@7e00f000 {
compatible = "samsung,s3c6410-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
};

76
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
View file

@ -1,76 +0,0 @@
* Samsung S3C64xx Clock Controller
The S3C64xx clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the S3C64xx family.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
- "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular S3C64xx SoC and this is specified where applicable.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "fin_pll" - PLL input clock (xtal/extclk) - required,
- "xusbxti" - USB xtal - required,
- "iiscdclk0" - I2S0 codec clock - optional,
- "iiscdclk1" - I2S1 codec clock - optional,
- "iiscdclk2" - I2S2 codec clock - optional,
- "pcmcdclk0" - PCM0 codec clock - optional,
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
Example: Clock controller node:
clock: clock-controller@7e00f000 {
compatible = "samsung,s3c6410-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
Example: Required external clocks:
fin_pll: clock-fin-pll {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
clock-frequency = <12000000>;
#clock-cells = <0>;
};
xusbxti: clock-xusbxti {
compatible = "fixed-clock";
clock-output-names = "xusbxti";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
uart0: serial@7f005000 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <5>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
<&clock SCLK_UART>;
};

92
drivers/clk/microchip/clk-mpfs.c
View file

@ -4,12 +4,10 @@
*
* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
*/
#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/microchip,mpfs-clock.h>
#include <soc/microchip/mpfs.h>
@ -361,93 +359,6 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c
return 0;
}
/*
* Peripheral clock resets
*/
#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
u32 mpfs_reset_read(struct device *dev)
{
struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR);
}
EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS);
void mpfs_reset_write(struct device *dev, u32 val)
{
struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR);
}
EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS);
static void mpfs_reset_unregister_adev(void *_adev)
{
struct auxiliary_device *adev = _adev;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
static void mpfs_reset_adev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
kfree(adev);
}
static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data)
{
struct auxiliary_device *adev;
int ret;
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
return ERR_PTR(-ENOMEM);
adev->name = "reset-mpfs";
adev->dev.parent = clk_data->dev;
adev->dev.release = mpfs_reset_adev_release;
adev->id = 666u;
ret = auxiliary_device_init(adev);
if (ret) {
kfree(adev);
return ERR_PTR(ret);
}
return adev;
}
static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
{
struct auxiliary_device *adev;
int ret;
adev = mpfs_reset_adev_alloc(clk_data);
if (IS_ERR(adev))
return PTR_ERR(adev);
ret = auxiliary_device_add(adev);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev);
}
#else /* !CONFIG_RESET_CONTROLLER */
static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
{
return 0;
}
#endif /* !CONFIG_RESET_CONTROLLER */
static int mpfs_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -499,7 +410,7 @@ static int mpfs_clk_probe(struct platform_device *pdev)
if (ret)
return ret;
return mpfs_reset_controller_register(clk_data);
return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
}
static const struct of_device_id mpfs_clk_of_match_table[] = {
@ -532,3 +443,4 @@ MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>");
MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
MODULE_IMPORT_NS(MCHP_CLK_MPFS);

2
drivers/clk/qcom/Kconfig
View file

@ -474,6 +474,7 @@ config SC_CAMCC_7280
config SC_CAMCC_8280XP
tristate "SC8280XP Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select SC_GCC_8280XP
help
Support for the camera clock controller on Qualcomm Technologies, Inc
@ -1094,6 +1095,7 @@ config SM_GPUCC_8550
config SM_GPUCC_8650
tristate "SM8650 Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_8650
help
Support for the graphics clock controller on SM8650 devices.

79
drivers/clk/qcom/apss-ipq-pll.c
View file

@ -8,43 +8,14 @@
#include "clk-alpha-pll.h"
/*
* Even though APSS PLL type is of existing one (like Huayra), its offsets
* are different from the one mentioned in the clk-alpha-pll.c, since the
* PLL is specific to APSS, so lets the define the same.
*/
static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
};
static struct clk_alpha_pll ipq_pll_huayra = {
.offset = 0x0,
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "a53pll",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
@ -55,14 +26,36 @@ static struct clk_alpha_pll ipq_pll_huayra = {
},
};
static struct clk_alpha_pll ipq_pll_stromer_plus = {
static struct clk_alpha_pll ipq_pll_stromer = {
.offset = 0x0,
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "a53pll",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static struct clk_alpha_pll ipq_pll_stromer_plus = {
.offset = 0x0,
/*
* The register offsets of the Stromer Plus PLL used in IPQ5332
* are the same as the Stromer PLL's offsets.
*/
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "a53pll",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
@ -73,8 +66,9 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
},
};
/* 1.008 GHz configuration */
static const struct alpha_pll_config ipq5018_pll_config = {
.l = 0x32,
.l = 0x2a,
.config_ctl_val = 0x4001075b,
.config_ctl_hi_val = 0x304,
.main_output_mask = BIT(0),
@ -144,30 +138,30 @@ struct apss_pll_data {
};
static const struct apss_pll_data ipq5018_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
.pll = &ipq_pll_stromer_plus,
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
.pll = &ipq_pll_stromer,
.pll_config = &ipq5018_pll_config,
};
static struct apss_pll_data ipq5332_pll_data = {
static const struct apss_pll_data ipq5332_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
.pll = &ipq_pll_stromer_plus,
.pll_config = &ipq5332_pll_config,
};
static struct apss_pll_data ipq8074_pll_data = {
static const struct apss_pll_data ipq8074_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq8074_pll_config,
};
static struct apss_pll_data ipq6018_pll_data = {
static const struct apss_pll_data ipq6018_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq6018_pll_config,
};
static struct apss_pll_data ipq9574_pll_data = {
static const struct apss_pll_data ipq9574_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq9574_pll_config,
@ -203,7 +197,8 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER ||
data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
ret = devm_clk_register_regmap(dev, &data->pll->clkr);

24
drivers/clk/qcom/clk-alpha-pll.c
View file

@ -83,6 +83,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
@ -213,10 +223,9 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0xff,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
[PLL_OFF_STATUS] = 0x28,
},
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[PLL_OFF_L_VAL] = 0x04,
@ -2114,6 +2123,15 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
{
u32 lval = config->l;
/*
* If the bootloader left the PLL enabled it's likely that there are
* RCGs that will lock up if we disable the PLL below.
*/
if (trion_pll_is_enabled(pll, regmap)) {
pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");
return;
}
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
@ -2490,6 +2508,8 @@ static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
a >> ALPHA_BITWIDTH);

5
drivers/clk/qcom/clk-alpha-pll.h
View file

@ -15,6 +15,7 @@
enum {
CLK_ALPHA_PLL_TYPE_DEFAULT,
CLK_ALPHA_PLL_TYPE_HUAYRA,
CLK_ALPHA_PLL_TYPE_HUAYRA_APSS,
CLK_ALPHA_PLL_TYPE_BRAMMO,
CLK_ALPHA_PLL_TYPE_FABIA,
CLK_ALPHA_PLL_TYPE_TRION,
@ -73,8 +74,10 @@ struct pll_vco {
/**
* struct clk_alpha_pll - phase locked loop (PLL)
* @offset: base address of registers
* @vco_table: array of VCO settings
* @regs: alpha pll register map (see @clk_alpha_pll_regs)
* @vco_table: array of VCO settings
* @num_vco: number of VCO settings in @vco_table
* @flags: bitmask to indicate features supported by the hardware
* @clkr: regmap clock handle
*/
struct clk_alpha_pll {

13
drivers/clk/qcom/clk-cbf-8996.c
View file

@ -41,17 +41,6 @@ enum {
#define CBF_PLL_OFFSET 0xf000
static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
[PLL_OFF_STATUS] = 0x28,
};
static struct alpha_pll_config cbfpll_config = {
.l = 72,
.config_ctl_val = 0x200d4828,
@ -67,7 +56,7 @@ static struct alpha_pll_config cbfpll_config = {
static struct clk_alpha_pll cbf_pll = {
.offset = CBF_PLL_OFFSET,
.regs = cbf_pll_regs,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "cbf_pll",

24
drivers/clk/qcom/clk-rcg.h
View file

@ -17,6 +17,23 @@ struct freq_tbl {
u16 n;
};
#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) }
#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } }
struct freq_conf {
u8 src;
u8 pre_div;
u16 m;
u16 n;
};
struct freq_multi_tbl {
unsigned long freq;
size_t num_confs;
const struct freq_conf *confs;
};
/**
* struct mn - M/N:D counter
* @mnctr_en_bit: bit to enable mn counter
@ -138,6 +155,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
* @safe_src_index: safe src index value
* @parent_map: map from software's parent index to hardware's src_sel field
* @freq_tbl: frequency table
* @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf
* @clkr: regmap clock handle
* @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
* @parked_cfg: cached value of the CFG register for parked RCGs
@ -149,7 +167,10 @@ struct clk_rcg2 {
u8 hid_width;
u8 safe_src_index;
const struct parent_map *parent_map;
const struct freq_tbl *freq_tbl;
union {
const struct freq_tbl *freq_tbl;
const struct freq_multi_tbl *freq_multi_tbl;
};
struct clk_regmap clkr;
u8 cfg_off;
u32 parked_cfg;
@ -169,6 +190,7 @@ struct clk_rcg2_gfx3d {
extern const struct clk_ops clk_rcg2_ops;
extern const struct clk_ops clk_rcg2_floor_ops;
extern const struct clk_ops clk_rcg2_fm_ops;
extern const struct clk_ops clk_rcg2_mux_closest_ops;
extern const struct clk_ops clk_edp_pixel_ops;
extern const struct clk_ops clk_byte_ops;

166
drivers/clk/qcom/clk-rcg2.c
View file

@ -260,6 +260,115 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
return 0;
}
static const struct freq_conf *
__clk_rcg2_select_conf(struct clk_hw *hw, const struct freq_multi_tbl *f,
unsigned long req_rate)
{
unsigned long rate_diff, best_rate_diff = ULONG_MAX;
const struct freq_conf *conf, *best_conf = NULL;
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const char *name = clk_hw_get_name(hw);
unsigned long parent_rate, rate;
struct clk_hw *p;
int index, i;
/* Exit early if only one config is defined */
if (f->num_confs == 1) {
best_conf = f->confs;
goto exit;
}
/* Search in each provided config the one that is near the wanted rate */
for (i = 0, conf = f->confs; i < f->num_confs; i++, conf++) {
index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
if (index < 0)
continue;
p = clk_hw_get_parent_by_index(hw, index);
if (!p)
continue;
parent_rate = clk_hw_get_rate(p);
rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
if (rate == req_rate) {
best_conf = conf;
goto exit;
}
rate_diff = abs_diff(req_rate, rate);
if (rate_diff < best_rate_diff) {
best_rate_diff = rate_diff;
best_conf = conf;
}
}
/*
* Very unlikely. Warn if we couldn't find a correct config
* due to parent not found in every config.
*/
if (unlikely(!best_conf)) {
WARN(1, "%s: can't find a configuration for rate %lu\n",
name, req_rate);
return ERR_PTR(-EINVAL);
}
exit:
return best_conf;
}
static int _freq_tbl_fm_determine_rate(struct clk_hw *hw, const struct freq_multi_tbl *f,
struct clk_rate_request *req)
{
unsigned long clk_flags, rate = req->rate;
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_conf *conf;
struct clk_hw *p;
int index;
f = qcom_find_freq_multi(f, rate);
if (!f || !f->confs)
return -EINVAL;
conf = __clk_rcg2_select_conf(hw, f, rate);
if (IS_ERR(conf))
return PTR_ERR(conf);
index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
if (index < 0)
return index;
clk_flags = clk_hw_get_flags(hw);
p = clk_hw_get_parent_by_index(hw, index);
if (!p)
return -EINVAL;
if (clk_flags & CLK_SET_RATE_PARENT) {
rate = f->freq;
if (conf->pre_div) {
if (!rate)
rate = req->rate;
rate /= 2;
rate *= conf->pre_div + 1;
}
if (conf->n) {
u64 tmp = rate;
tmp = tmp * conf->n;
do_div(tmp, conf->m);
rate = tmp;
}
} else {
rate = clk_hw_get_rate(p);
}
req->best_parent_hw = p;
req->best_parent_rate = rate;
req->rate = f->freq;
return 0;
}
static int clk_rcg2_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
@ -276,6 +385,14 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
}
static int clk_rcg2_fm_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req);
}
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
u32 *_cfg)
{
@ -371,6 +488,30 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
return clk_rcg2_configure(rcg, f);
}
static int __clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_multi_tbl *f;
const struct freq_conf *conf;
struct freq_tbl f_tbl = {};
f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate);
if (!f || !f->confs)
return -EINVAL;
conf = __clk_rcg2_select_conf(hw, f, rate);
if (IS_ERR(conf))
return PTR_ERR(conf);
f_tbl.freq = f->freq;
f_tbl.src = conf->src;
f_tbl.pre_div = conf->pre_div;
f_tbl.m = conf->m;
f_tbl.n = conf->n;
return clk_rcg2_configure(rcg, &f_tbl);
}
static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@ -383,6 +524,12 @@ static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
return __clk_rcg2_set_rate(hw, rate, FLOOR);
}
static int clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return __clk_rcg2_fm_set_rate(hw, rate);
}
static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
@ -395,6 +542,12 @@ static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
return __clk_rcg2_set_rate(hw, rate, FLOOR);
}
static int clk_rcg2_fm_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return __clk_rcg2_fm_set_rate(hw, rate);
}
static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@ -505,6 +658,19 @@ const struct clk_ops clk_rcg2_floor_ops = {
};
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
const struct clk_ops clk_rcg2_fm_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.determine_rate = clk_rcg2_fm_determine_rate,
.set_rate = clk_rcg2_fm_set_rate,
.set_rate_and_parent = clk_rcg2_fm_set_rate_and_parent,
.get_duty_cycle = clk_rcg2_get_duty_cycle,
.set_duty_cycle = clk_rcg2_set_duty_cycle,
};
EXPORT_SYMBOL_GPL(clk_rcg2_fm_ops);
const struct clk_ops clk_rcg2_mux_closest_ops = {
.determine_rate = __clk_mux_determine_rate_closest,
.get_parent = clk_rcg2_get_parent,

1
drivers/clk/qcom/clk-rpm.c
View file

@ -98,7 +98,6 @@ struct clk_rpm {
};
struct rpm_cc {
struct qcom_rpm *rpm;
struct clk_rpm **clks;
size_t num_clks;
u32 xo_buffer_value;

18
drivers/clk/qcom/common.c
View file

@ -41,6 +41,24 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
}
EXPORT_SYMBOL_GPL(qcom_find_freq);
const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
unsigned long rate)
{
if (!f)
return NULL;
if (!f->freq)
return f;
for (; f->freq; f++)
if (rate <= f->freq)
return f;
/* Default to our fastest rate */
return f - 1;
}
EXPORT_SYMBOL_GPL(qcom_find_freq_multi);
const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
unsigned long rate)
{

2
drivers/clk/qcom/common.h
View file

@ -45,6 +45,8 @@ extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate);
extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
unsigned long rate);
extern const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
unsigned long rate);
extern void
qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,

11
drivers/clk/qcom/dispcc-sm6350.c
View file

@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.cmd_rcgr = 0x10f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};

20
drivers/clk/qcom/dispcc-sm8450.c
View file

@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x819c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};

20
drivers/clk/qcom/dispcc-sm8550.c
View file

@ -345,26 +345,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x8170,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -418,13 +409,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -478,13 +468,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -538,13 +527,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};

20
drivers/clk/qcom/dispcc-sm8650.c
View file

@ -343,26 +343,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x8170,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -416,13 +407,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -476,13 +466,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -536,13 +525,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};

120
drivers/clk/qcom/gcc-ipq8074.c
View file

@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = {
},
};
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
C(P_UNIPHY1_RX, 12.5, 0, 0),
C(P_UNIPHY0_RX, 5, 0, 0),
};
static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
C(P_UNIPHY1_RX, 2.5, 0, 0),
C(P_UNIPHY0_RX, 1, 0, 0),
};
static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
FMS(19200000, P_XO, 1, 0, 0),
FM(25000000, ftbl_nss_port5_rx_clk_src_25),
FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
FM(125000000, ftbl_nss_port5_rx_clk_src_125),
FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
{ }
};
@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
static struct clk_rcg2 nss_port5_rx_clk_src = {
.cmd_rcgr = 0x68060,
.freq_tbl = ftbl_nss_port5_rx_clk_src,
.freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_fm_ops,
},
};
@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = {
},
};
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
C(P_UNIPHY1_TX, 12.5, 0, 0),
C(P_UNIPHY0_TX, 5, 0, 0),
};
static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
C(P_UNIPHY1_TX, 2.5, 0, 0),
C(P_UNIPHY0_TX, 1, 0, 0),
};
static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
FMS(19200000, P_XO, 1, 0, 0),
FM(25000000, ftbl_nss_port5_tx_clk_src_25),
FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
FM(125000000, ftbl_nss_port5_tx_clk_src_125),
FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
{ }
};
@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
static struct clk_rcg2 nss_port5_tx_clk_src = {
.cmd_rcgr = 0x68068,
.freq_tbl = ftbl_nss_port5_tx_clk_src,
.freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_fm_ops,
},
};
@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = {
},
};
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY2_RX, 5, 0, 0),
F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
F(125000000, P_UNIPHY2_RX, 1, 0, 0),
F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
C(P_UNIPHY2_RX, 5, 0, 0),
C(P_UNIPHY2_RX, 12.5, 0, 0),
};
static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
C(P_UNIPHY2_RX, 1, 0, 0),
C(P_UNIPHY2_RX, 2.5, 0, 0),
};
static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = {
FMS(19200000, P_XO, 1, 0, 0),
FM(25000000, ftbl_nss_port6_rx_clk_src_25),
FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
FM(125000000, ftbl_nss_port6_rx_clk_src_125),
FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
{ }
};
@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
static struct clk_rcg2 nss_port6_rx_clk_src = {
.cmd_rcgr = 0x68070,
.freq_tbl = ftbl_nss_port6_rx_clk_src,
.freq_multi_tbl = ftbl_nss_port6_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_clk_src",
.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_fm_ops,
},
};
@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = {
},
};
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY2_TX, 5, 0, 0),
F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
F(125000000, P_UNIPHY2_TX, 1, 0, 0),
F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
C(P_UNIPHY2_TX, 5, 0, 0),
C(P_UNIPHY2_TX, 12.5, 0, 0),
};
static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
C(P_UNIPHY2_TX, 1, 0, 0),
C(P_UNIPHY2_TX, 2.5, 0, 0),
};
static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = {
FMS(19200000, P_XO, 1, 0, 0),
FM(25000000, ftbl_nss_port6_tx_clk_src_25),
FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
FM(125000000, ftbl_nss_port6_tx_clk_src_125),
FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
{ }
};
@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
static struct clk_rcg2 nss_port6_tx_clk_src = {
.cmd_rcgr = 0x68078,
.freq_tbl = ftbl_nss_port6_tx_clk_src,
.freq_multi_tbl = ftbl_nss_port6_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_clk_src",
.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_fm_ops,
},
};

1
drivers/clk/qcom/gcc-msm8917.c
View file

@ -3278,6 +3278,7 @@ static const struct of_device_id gcc_msm8917_match_table[] = {
{ .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
{},
};
MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table);
static struct platform_driver gcc_msm8917_driver = {
.probe = gcc_msm8917_probe,

1
drivers/clk/qcom/gcc-msm8953.c
View file

@ -4227,6 +4227,7 @@ static const struct of_device_id gcc_msm8953_match_table[] = {
{ .compatible = "qcom,gcc-msm8953" },
{},
};
MODULE_DEVICE_TABLE(of, gcc_msm8953_match_table);
static struct platform_driver gcc_msm8953_driver = {
.probe = gcc_msm8953_probe,

61
drivers/clk/qcom/gcc-sm8150.c
View file

@ -207,28 +207,6 @@ static const struct clk_parent_data gcc_parents_7[] = {
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
@ -1361,24 +1339,6 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
},
};
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw },
.num_parents = 1,
/* required for cpuss */
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_dvm_bus_clk = {
.halt_reg = 0x48190,
.halt_check = BRANCH_HALT,
@ -2685,24 +2645,6 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x4819c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw },
.num_parents = 1,
/* required for cpuss */
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
@ -3550,8 +3492,6 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
@ -3669,7 +3609,6 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,

6
drivers/clk/qcom/hfpll.c
View file

@ -14,7 +14,7 @@
#include "clk-regmap.h"
#include "clk-hfpll.h"
static const struct hfpll_data hdata = {
static const struct hfpll_data qcs404 = {
.mode_reg = 0x00,
.l_reg = 0x04,
.m_reg = 0x08,
@ -84,10 +84,12 @@ static const struct hfpll_data msm8976_cci = {
};
static const struct of_device_id qcom_hfpll_match_table[] = {
{ .compatible = "qcom,hfpll", .data = &hdata },
{ .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
{ .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
{ .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
{ .compatible = "qcom,qcs404-hfpll", .data = &qcs404 },
/* Deprecated in bindings */
{ .compatible = "qcom,hfpll", .data = &qcs404 },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);

8
drivers/clk/qcom/mmcc-msm8998.c
View file

@ -2535,6 +2535,8 @@ static struct clk_branch vmem_ahb_clk = {
static struct gdsc video_top_gdsc = {
.gdscr = 0x1024,
.cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
.cxc_count = 3,
.pd = {
.name = "video_top",
},
@ -2543,20 +2545,26 @@ static struct gdsc video_top_gdsc = {
static struct gdsc video_subcore0_gdsc = {
.gdscr = 0x1040,
.cxcs = (unsigned int []){ 0x1048 },
.cxc_count = 1,
.pd = {
.name = "video_subcore0",
},
.parent = &video_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc video_subcore1_gdsc = {
.gdscr = 0x1044,
.cxcs = (unsigned int []){ 0x104c },
.cxc_count = 1,
.pd = {
.name = "video_subcore1",
},
.parent = &video_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc mdss_gdsc = {

56
drivers/clk/samsung/clk-exynos-arm64.c
View file

@ -17,10 +17,17 @@
#include "clk-exynos-arm64.h"
/* PLL register bits */
#define PLL_CON1_MANUAL BIT(1)
/* Gate register bits */
#define GATE_MANUAL BIT(20)
#define GATE_ENABLE_HWACG BIT(28)
/* PLL_CONx_PLL register offsets range */
#define PLL_CON_OFF_START 0x100
#define PLL_CON_OFF_END 0x600
/* Gate register offsets range */
#define GATE_OFF_START 0x2000
#define GATE_OFF_END 0x2fff
@ -38,17 +45,36 @@ struct exynos_arm64_cmu_data {
struct samsung_clk_provider *ctx;
};
/* Check if the register offset is a GATE register */
static bool is_gate_reg(unsigned long off)
{
return off >= GATE_OFF_START && off <= GATE_OFF_END;
}
/* Check if the register offset is a PLL_CONx register */
static bool is_pll_conx_reg(unsigned long off)
{
return off >= PLL_CON_OFF_START && off <= PLL_CON_OFF_END;
}
/* Check if the register offset is a PLL_CON1 register */
static bool is_pll_con1_reg(unsigned long off)
{
return is_pll_conx_reg(off) && (off & 0xf) == 0x4 && !(off & 0x10);
}
/**
* exynos_arm64_init_clocks - Set clocks initial configuration
* @np: CMU device tree node with "reg" property (CMU addr)
* @reg_offs: Register offsets array for clocks to init
* @reg_offs_len: Number of register offsets in reg_offs array
* @np: CMU device tree node with "reg" property (CMU addr)
* @cmu: CMU data
*
* Set manual control mode for all gate clocks.
* Set manual control mode for all gate and PLL clocks.
*/
static void __init exynos_arm64_init_clocks(struct device_node *np,
const unsigned long *reg_offs, size_t reg_offs_len)
const struct samsung_cmu_info *cmu)
{
const unsigned long *reg_offs = cmu->clk_regs;
size_t reg_offs_len = cmu->nr_clk_regs;
void __iomem *reg_base;
size_t i;
@ -60,14 +86,14 @@ static void __init exynos_arm64_init_clocks(struct device_node *np,
void __iomem *reg = reg_base + reg_offs[i];
u32 val;
/* Modify only gate clock registers */
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
continue;
val = readl(reg);
val |= GATE_MANUAL;
val &= ~GATE_ENABLE_HWACG;
writel(val, reg);
if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) {
writel(PLL_CON1_MANUAL, reg);
} else if (is_gate_reg(reg_offs[i])) {
val = readl(reg);
val |= GATE_MANUAL;
val &= ~GATE_ENABLE_HWACG;
writel(val, reg);
}
}
iounmap(reg_base);
@ -177,7 +203,7 @@ void __init exynos_arm64_register_cmu(struct device *dev,
pr_err("%s: could not enable bus clock %s; err = %d\n",
__func__, cmu->clk_name, err);
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
exynos_arm64_init_clocks(np, cmu);
samsung_cmu_register_one(np, cmu);
}
@ -224,7 +250,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev,
__func__, cmu->clk_name, ret);
if (set_manual)
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
exynos_arm64_init_clocks(np, cmu);
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))

440
drivers/clk/samsung/clk-exynos850.c
View file

@ -14,13 +14,16 @@
#include <dt-bindings/clock/exynos850.h>
#include "clk.h"
#include "clk-cpu.h"
#include "clk-exynos-arm64.h"
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
#define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
#define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
#define CLKS_NR_CPUCL1 (CLK_CLUSTER1_SCLK + 1)
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
@ -47,6 +50,10 @@
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
@ -69,6 +76,10 @@
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
#define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
#define CLK_CON_DIV_CLKCMU_DPU 0x1840
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
@ -97,6 +108,10 @@
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
@ -130,6 +145,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_DPU,
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
@ -152,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
CLK_CON_DIV_CLKCMU_CORE_SSS,
CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
CLK_CON_DIV_CLKCMU_CPUCL1_DBG,
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
CLK_CON_DIV_CLKCMU_DPU,
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
CLK_CON_DIV_CLKCMU_HSI_BUS,
@ -180,6 +203,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG,
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_DPU,
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
@ -234,6 +261,14 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
"oscclk", "oscclk" };
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
PNAME(mout_cpucl0_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
"dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_cpucl0_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
PNAME(mout_cpucl1_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
"dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_cpucl1_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
@ -300,6 +335,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
/* CPUCL0 */
MUX(CLK_MOUT_CPUCL0_DBG, "mout_cpucl0_dbg", mout_cpucl0_dbg_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cpucl0_switch", mout_cpucl0_switch_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
/* CPUCL1 */
MUX(CLK_MOUT_CPUCL1_DBG, "mout_cpucl1_dbg", mout_cpucl1_dbg_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cpucl1_switch", mout_cpucl1_switch_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
/* DPU */
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
@ -378,6 +425,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
/* CPUCL0 */
DIV(CLK_DOUT_CPUCL0_DBG, "dout_cpucl0_dbg", "gout_cpucl0_dbg",
CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cpucl0_switch", "gout_cpucl0_switch",
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
/* CPUCL1 */
DIV(CLK_DOUT_CPUCL1_DBG, "dout_cpucl1_dbg", "gout_cpucl1_dbg",
CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cpucl1_switch", "gout_cpucl1_switch",
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
/* DPU */
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
CLK_CON_DIV_CLKCMU_DPU, 0, 4),
@ -442,6 +501,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
/* CPUCL0 */
GATE(CLK_GOUT_CPUCL0_DBG, "gout_cpucl0_dbg", "mout_cpucl0_dbg",
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cpucl0_switch", "mout_cpucl0_switch",
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
/* CPUCL1 */
GATE(CLK_GOUT_CPUCL1_DBG, "gout_cpucl1_dbg", "mout_cpucl1_dbg",
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cpucl1_switch", "mout_cpucl1_switch",
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
/* DPU */
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
@ -1030,6 +1101,373 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
.clk_name = "gout_clkcmu_cmgp_bus",
};
/* ---- CMU_CPUCL0 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
#define PLL_CON0_PLL_CPUCL0 0x0100
#define PLL_CON1_PLL_CPUCL0 0x0104
#define PLL_CON3_PLL_CPUCL0 0x010c
#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
#define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
#define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
#define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
static const unsigned long cpucl0_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_CPUCL0,
PLL_CON0_PLL_CPUCL0,
PLL_CON1_PLL_CPUCL0,
PLL_CON3_PLL_CPUCL0,
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK,
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK,
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK,
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
};
/* List of parent clocks for Muxes in CMU_CPUCL0 */
PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_cpucl0_switch" };
PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_cpucl0_dbg" };
PNAME(mout_cpucl0_pll_p) = { "mout_pll_cpucl0",
"mout_cpucl0_switch_user" };
static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
PLL_35XX_RATE(26 * MHZ, 949000000U, 219, 3, 1),
PLL_35XX_RATE(26 * MHZ, 806000000U, 186, 3, 1),
PLL_35XX_RATE(26 * MHZ, 650000000U, 150, 3, 1),
PLL_35XX_RATE(26 * MHZ, 546000000U, 252, 3, 2),
PLL_35XX_RATE(26 * MHZ, 442000000U, 204, 3, 2),
PLL_35XX_RATE(26 * MHZ, 351000000U, 162, 3, 2),
PLL_35XX_RATE(26 * MHZ, 247000000U, 114, 3, 2),
PLL_35XX_RATE(26 * MHZ, 182000000U, 168, 3, 3),
PLL_35XX_RATE(26 * MHZ, 130000000U, 120, 3, 3),
};
static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
PLL(pll_0822x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
};
static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
PLL_CON0_PLL_CPUCL0, 4, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX_F(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user",
mout_cpucl0_switch_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1,
CLK_SET_RATE_PARENT, 0),
MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user",
mout_cpucl0_dbg_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
MUX_F(CLK_MOUT_CPUCL0_PLL, "mout_cpucl0_pll", mout_cpucl0_pll_p,
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
DIV_F(CLK_DOUT_CPUCL0_CPU, "dout_cpucl0_cpu", "mout_cpucl0_pll",
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL0_CMUREF, "dout_cpucl0_cmuref", "dout_cpucl0_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL0_PCLK, "dout_cpucl0_pclk", "dout_cpucl0_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
/* EMBEDDED_CMU_CPUCL0 */
DIV_F(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", "gout_cluster0_cpu",
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER0_PCLKDBG, "dout_cluster0_pclkdbg",
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
};
static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
GATE(CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK, "gout_cpucl0_cmu_cpucl0_pclk",
"dout_cpucl0_pclk",
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
/* EMBEDDED_CMU_CPUCL0 */
GATE(CLK_GOUT_CLUSTER0_CPU, "gout_cluster0_cpu", "dout_cpucl0_cpu",
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_SCLK, "gout_cluster0_sclk", "gout_cluster0_cpu",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_ATCLK, "gout_cluster0_atclk",
"dout_cluster0_atclk",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_PERIPHCLK, "gout_cluster0_periphclk",
"dout_cluster0_periphclk",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER0_PCLK, "gout_cluster0_pclk",
"dout_cluster0_pclkdbg",
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
/*
* Each parameter is going to be written into the corresponding DIV register. So
* the actual divider value for each parameter will be 1/(param+1). All these
* parameters must be in the range of 0..15, as the divider range for all of
* these DIV clocks is 1..16. The default values for these dividers is
* (1, 3, 3, 1).
*/
#define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) \
(((aclk) << 16) | ((atclk) << 12) | ((pclkdbg) << 8) | \
((periphclk) << 4))
static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst
= {
{ 2210000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 2106000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 2002000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1846000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1742000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1586000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1456000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1300000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1157000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 1053000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 949000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 806000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 650000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 546000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 442000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 351000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 247000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 182000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 130000, E850_CPU_DIV0(1, 3, 3, 1) },
{ 0 }
};
static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = {
CPU_CLK(CLK_CLUSTER0_SCLK, "cluster0_clk", CLK_MOUT_PLL_CPUCL0,
CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
exynos850_cluster_clk_d),
};
static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
.pll_clks = cpucl0_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
.mux_clks = cpucl0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
.div_clks = cpucl0_div_clks,
.nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
.gate_clks = cpucl0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
.cpu_clks = cpucl0_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(cpucl0_cpu_clks),
.nr_clk_ids = CLKS_NR_CPUCL0,
.clk_regs = cpucl0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
.clk_name = "dout_cpucl0_switch",
.manual_plls = true,
};
static void __init exynos850_cmu_cpucl0_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
}
/* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0",
exynos850_cmu_cpucl0_init);
/* ---- CMU_CPUCL1 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
#define PLL_CON0_PLL_CPUCL1 0x0100
#define PLL_CON1_PLL_CPUCL1 0x0104
#define PLL_CON3_PLL_CPUCL1 0x010c
#define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
#define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
#define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
static const unsigned long cpucl1_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_CPUCL1,
PLL_CON0_PLL_CPUCL1,
PLL_CON1_PLL_CPUCL1,
PLL_CON3_PLL_CPUCL1,
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER,
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG,
CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK,
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK,
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK,
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
};
/* List of parent clocks for Muxes in CMU_CPUCL0 */
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
PNAME(mout_cpucl1_pll_p) = { "mout_pll_cpucl1",
"mout_cpucl1_switch_user" };
static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
PLL(pll_0822x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
};
static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
PLL_CON0_PLL_CPUCL1, 4, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX_F(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user",
mout_cpucl1_switch_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1,
CLK_SET_RATE_PARENT, 0),
MUX(CLK_MOUT_CPUCL1_DBG_USER, "mout_cpucl1_dbg_user",
mout_cpucl1_dbg_user_p,
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER, 4, 1),
MUX_F(CLK_MOUT_CPUCL1_PLL, "mout_cpucl1_pll", mout_cpucl1_pll_p,
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
DIV_F(CLK_DOUT_CPUCL1_CPU, "dout_cpucl1_cpu", "mout_cpucl1_pll",
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL1_CMUREF, "dout_cpucl1_cmuref", "dout_cpucl1_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CPUCL1_PCLK, "dout_cpucl1_pclk", "dout_cpucl1_cpu",
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
/* EMBEDDED_CMU_CPUCL1 */
DIV_F(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", "gout_cluster1_cpu",
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER1_PCLKDBG, "dout_cluster1_pclkdbg",
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
};
static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
GATE(CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK, "gout_cpucl1_cmu_cpucl1_pclk",
"dout_cpucl1_pclk",
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
/* EMBEDDED_CMU_CPUCL1 */
GATE(CLK_GOUT_CLUSTER1_CPU, "gout_cluster1_cpu", "dout_cpucl1_cpu",
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_SCLK, "gout_cluster1_sclk", "gout_cluster1_cpu",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_ATCLK, "gout_cluster1_atclk",
"dout_cluster1_atclk",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_PERIPHCLK, "gout_cluster1_periphclk",
"dout_cluster1_periphclk",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CLUSTER1_PCLK, "gout_cluster1_pclk",
"dout_cluster1_pclkdbg",
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = {
CPU_CLK(CLK_CLUSTER1_SCLK, "cluster1_clk", CLK_MOUT_PLL_CPUCL1,
CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
exynos850_cluster_clk_d),
};
static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
.pll_clks = cpucl1_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
.mux_clks = cpucl1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
.div_clks = cpucl1_div_clks,
.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
.gate_clks = cpucl1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
.cpu_clks = cpucl1_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(cpucl1_cpu_clks),
.nr_clk_ids = CLKS_NR_CPUCL1,
.clk_regs = cpucl1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
.clk_name = "dout_cpucl1_switch",
.manual_plls = true,
};
static void __init exynos850_cmu_cpucl1_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
}
/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1",
exynos850_cmu_cpucl1_init);
/* ---- CMU_G3D ------------------------------------------------------------- */
/* Register Offset definitions for CMU_G3D (0x11400000) */

8
drivers/clk/samsung/clk-exynosautov9.c
View file

@ -352,13 +352,13 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
};

1192
drivers/clk/samsung/clk-gs101.c
View file

File diff suppressed because it is too large Load diff

11
drivers/clk/samsung/clk.c
View file

@ -139,7 +139,7 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
unsigned int nr_clk)
{
struct clk_hw *clk_hw;
unsigned int idx, ret;
unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) {
clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
@ -151,15 +151,6 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
}
samsung_clk_add_lookup(ctx, clk_hw, list->id);
/*
* Unconditionally add a clock lookup for the fixed rate clocks.
* There are not many of these on any of Samsung platforms.
*/
ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
if (ret)
pr_err("%s: failed to register clock lookup for %s",
__func__, list->name);
}
}

15
drivers/clk/samsung/clk.h
View file

@ -133,7 +133,7 @@ struct samsung_mux_clock {
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = (f) | CLK_SET_RATE_NO_REPARENT, \
.flags = f, \
.offset = o, \
.shift = s, \
.width = w, \
@ -141,9 +141,16 @@ struct samsung_mux_clock {
}
#define MUX(_id, cname, pnames, o, s, w) \
__MUX(_id, cname, pnames, o, s, w, 0, 0)
__MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0)
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
__MUX(_id, cname, pnames, o, s, w, (f) | CLK_SET_RATE_NO_REPARENT, mf)
/* Used by MUX clocks where reparenting on clock rate change is allowed. */
#define nMUX(_id, cname, pnames, o, s, w) \
__MUX(_id, cname, pnames, o, s, w, 0, 0)
#define nMUX_F(_id, cname, pnames, o, s, w, f, mf) \
__MUX(_id, cname, pnames, o, s, w, f, mf)
/**
@ -330,6 +337,7 @@ struct samsung_clock_reg_cache {
* @suspend_regs: list of clock registers to set before suspend
* @nr_suspend_regs: count of clock registers in @suspend_regs
* @clk_name: name of the parent clock needed for CMU register access
* @manual_plls: Enable manual control for PLL clocks
*/
struct samsung_cmu_info {
const struct samsung_pll_clock *pll_clks;
@ -354,6 +362,9 @@ struct samsung_cmu_info {
const struct samsung_clk_reg_dump *suspend_regs;
unsigned int nr_suspend_regs;
const char *clk_name;
/* ARM64 Exynos CMUs */
bool manual_plls;
};
struct samsung_clk_provider *samsung_clk_init(struct device *dev,

95
drivers/reset/reset-mpfs.c
View file

@ -8,9 +8,11 @@
*/
#include <linux/auxiliary_bus.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/microchip,mpfs-clock.h>
#include <soc/microchip/mpfs.h>
@ -28,20 +30,30 @@
/* block concurrent access to the soft reset register */
static DEFINE_SPINLOCK(mpfs_reset_lock);
struct mpfs_reset {
void __iomem *base;
struct reset_controller_dev rcdev;
};
static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct mpfs_reset, rcdev);
}
/*
* Peripheral clock resets
*/
static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
unsigned long flags;
u32 reg;
spin_lock_irqsave(&mpfs_reset_lock, flags);
reg = mpfs_reset_read(rcdev->dev);
reg = readl(rst->base);
reg |= BIT(id);
mpfs_reset_write(rcdev->dev, reg);
writel(reg, rst->base);
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
@ -50,14 +62,15 @@ static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
unsigned long flags;
u32 reg;
spin_lock_irqsave(&mpfs_reset_lock, flags);
reg = mpfs_reset_read(rcdev->dev);
reg = readl(rst->base);
reg &= ~BIT(id);
mpfs_reset_write(rcdev->dev, reg);
writel(reg, rst->base);
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
@ -66,7 +79,8 @@ static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
{
u32 reg = mpfs_reset_read(rcdev->dev);
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
u32 reg = readl(rst->base);
/*
* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
@ -121,11 +135,15 @@ static int mpfs_reset_probe(struct auxiliary_device *adev,
{
struct device *dev = &adev->dev;
struct reset_controller_dev *rcdev;
struct mpfs_reset *rst;
rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL);
if (!rcdev)
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
if (!rst)
return -ENOMEM;
rst->base = (void __iomem *)adev->dev.platform_data;
rcdev = &rst->rcdev;
rcdev->dev = dev;
rcdev->dev->parent = dev->parent;
rcdev->ops = &mpfs_reset_ops;
@ -137,9 +155,68 @@ static int mpfs_reset_probe(struct auxiliary_device *adev,
return devm_reset_controller_register(dev, rcdev);
}
static void mpfs_reset_unregister_adev(void *_adev)
{
struct auxiliary_device *adev = _adev;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
static void mpfs_reset_adev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
kfree(adev);
}
static struct auxiliary_device *mpfs_reset_adev_alloc(struct device *clk_dev)
{
struct auxiliary_device *adev;
int ret;
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
return ERR_PTR(-ENOMEM);
adev->name = "reset-mpfs";
adev->dev.parent = clk_dev;
adev->dev.release = mpfs_reset_adev_release;
adev->id = 666u;
ret = auxiliary_device_init(adev);
if (ret) {
kfree(adev);
return ERR_PTR(ret);
}
return adev;
}
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base)
{
struct auxiliary_device *adev;
int ret;
adev = mpfs_reset_adev_alloc(clk_dev);
if (IS_ERR(adev))
return PTR_ERR(adev);
ret = auxiliary_device_add(adev);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
adev->dev.platform_data = (__force void *)base;
return devm_add_action_or_reset(clk_dev, mpfs_reset_unregister_adev, adev);
}
EXPORT_SYMBOL_NS_GPL(mpfs_reset_controller_register, MCHP_CLK_MPFS);
static const struct auxiliary_device_id mpfs_reset_ids[] = {
{
.name = "clk_mpfs.reset-mpfs",
.name = "reset_mpfs.reset-mpfs",
},
{ }
};

116
include/dt-bindings/clock/google,gs101.h
View file

@ -313,6 +313,122 @@
#define CLK_APM_PLL_DIV4_APM 70
#define CLK_APM_PLL_DIV16_APM 71
/* CMU_HSI0 */
#define CLK_FOUT_USB_PLL 1
#define CLK_MOUT_PLL_USB 2
#define CLK_MOUT_HSI0_ALT_USER 3
#define CLK_MOUT_HSI0_BUS_USER 4
#define CLK_MOUT_HSI0_DPGTC_USER 5
#define CLK_MOUT_HSI0_TCXO_USER 6
#define CLK_MOUT_HSI0_USB20_USER 7
#define CLK_MOUT_HSI0_USB31DRD_USER 8
#define CLK_MOUT_HSI0_USBDPDBG_USER 9
#define CLK_MOUT_HSI0_BUS 10
#define CLK_MOUT_HSI0_USB20_REF 11
#define CLK_MOUT_HSI0_USB31DRD 12
#define CLK_DOUT_HSI0_USB31DRD 13
#define CLK_GOUT_HSI0_PCLK 14
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26 15
#define CLK_GOUT_HSI0_CLK_HSI0_ALT 16
#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK 17
#define CLK_GOUT_HSI0_DP_LINK_I_PCLK 18
#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 19
#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK 20
#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK 21
#define CLK_GOUT_HSI0_GPC_HSI0_PCLK 22
#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK 23
#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK 24
#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK 25
#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK 26
#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK 27
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK 28
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK 29
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK 30
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK 31
#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 32
#define CLK_GOUT_HSI0_SSMT_USB_ACLK 33
#define CLK_GOUT_HSI0_SSMT_USB_PCLK 34
#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 35
#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 36
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK 37
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK 38
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK 39
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK 40
#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 41
#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 42
#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26 43
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40 44
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL 45
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK 46
#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK 47
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK 48
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK 49
#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK 50
#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51
#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52
/* CMU_HSI2 */
#define CLK_MOUT_HSI2_BUS_USER 1
#define CLK_MOUT_HSI2_MMC_CARD_USER 2
#define CLK_MOUT_HSI2_PCIE_USER 3
#define CLK_MOUT_HSI2_UFS_EMBD_USER 4
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10
#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11
#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12
#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13
#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14
#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15
#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16
#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17
#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29
#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30
#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31
#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42
#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43
#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44
#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45
#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46
#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55
#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56
#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57
#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58
#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59
#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60
/* CMU_MISC */
#define CLK_MOUT_MISC_BUS_USER 1
#define CLK_MOUT_MISC_SSS_USER 2

10
include/soc/microchip/mpfs.h
View file

@ -43,11 +43,11 @@ struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_
#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
u32 mpfs_reset_read(struct device *dev);
void mpfs_reset_write(struct device *dev, u32 val);
#if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC)
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base);
#else
static inline int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) { return 0; }
#endif /* if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) */
#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
#endif /* __SOC_MPFS_H__ */