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MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.
The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64 so we change its type to unsigned long. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10644/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -20,7 +20,7 @@ int mips_cm_is64;
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phys_addr_t __mips_cm_phys_base(void)
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{
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u32 config3 = read_c0_config3();
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u32 cmgcr;
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unsigned long cmgcr;
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/* Check the CMGCRBase register is implemented */
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if (!(config3 & MIPS_CONF3_CMGCR))
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