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clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -99,7 +99,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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od_enc = ctl >> pll_info->od_shift;
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od_enc = ctl >> pll_info->od_shift;
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od_enc &= GENMASK(pll_info->od_bits - 1, 0);
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od_enc &= GENMASK(pll_info->od_bits - 1, 0);
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if (!pll_info->no_bypass_bit) {
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if (pll_info->bypass_bit >= 0) {
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ctl = readl(cgu->base + pll_info->bypass_reg);
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ctl = readl(cgu->base + pll_info->bypass_reg);
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bypass = !!(ctl & BIT(pll_info->bypass_bit));
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bypass = !!(ctl & BIT(pll_info->bypass_bit));
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@ -226,7 +226,7 @@ static int ingenic_pll_enable(struct clk_hw *hw)
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u32 ctl;
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u32 ctl;
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spin_lock_irqsave(&cgu->lock, flags);
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spin_lock_irqsave(&cgu->lock, flags);
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if (!pll_info->no_bypass_bit) {
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if (pll_info->bypass_bit >= 0) {
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ctl = readl(cgu->base + pll_info->bypass_reg);
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ctl = readl(cgu->base + pll_info->bypass_reg);
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ctl &= ~BIT(pll_info->bypass_bit);
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ctl &= ~BIT(pll_info->bypass_bit);
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@ -39,10 +39,10 @@
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* their encoded values in the PLL control register, or -1 for
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* their encoded values in the PLL control register, or -1 for
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* unsupported values
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* unsupported values
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* @bypass_reg: the offset of the bypass control register within the CGU
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* @bypass_reg: the offset of the bypass control register within the CGU
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* @bypass_bit: the index of the bypass bit in the PLL control register
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* @bypass_bit: the index of the bypass bit in the PLL control register, or
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* -1 if there is no bypass bit
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* @enable_bit: the index of the enable bit in the PLL control register
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* @enable_bit: the index of the enable bit in the PLL control register
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* @stable_bit: the index of the stable bit in the PLL control register
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* @stable_bit: the index of the stable bit in the PLL control register
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* @no_bypass_bit: if set, the PLL has no bypass functionality
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*/
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*/
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struct ingenic_cgu_pll_info {
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struct ingenic_cgu_pll_info {
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unsigned reg;
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unsigned reg;
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@ -52,10 +52,9 @@ struct ingenic_cgu_pll_info {
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u8 n_shift, n_bits, n_offset;
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u8 n_shift, n_bits, n_offset;
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u8 od_shift, od_bits, od_max;
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u8 od_shift, od_bits, od_max;
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unsigned bypass_reg;
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unsigned bypass_reg;
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u8 bypass_bit;
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s8 bypass_bit;
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u8 enable_bit;
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u8 enable_bit;
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u8 stable_bit;
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u8 stable_bit;
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bool no_bypass_bit;
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};
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};
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/**
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/**
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@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
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.od_bits = 2,
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.od_bits = 2,
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.od_max = 8,
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.od_max = 8,
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.od_encoding = pll_od_encoding,
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.od_encoding = pll_od_encoding,
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.bypass_reg = CGU_REG_CPPCR1,
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.bypass_bit = -1,
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.no_bypass_bit = true,
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.enable_bit = 7,
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.enable_bit = 7,
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.stable_bit = 6,
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.stable_bit = 6,
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},
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},
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