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iommu/vt-d: Disallow read-only mappings to nest parent domain
When remapping hardware is configured by system software in scalable mode as Nested (PGTT=011b) and with PWSNP field Set in the PASID-table-entry, it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled) in first-stage page-table entries even when second-stage mappings indicate that corresponding first-stage page-table is Read-Only. As the result, contents of pages designated by VMM as Read-Only can be modified by IOMMU via PML5E (PML4E for 4-level tables) access as part of address translation process due to DMAs issued by Guest. This disallows read-only mappings in the domain that is supposed to be used as nested parent. Reference from Sapphire Rapids Specification Update [1], errata details, SPR17. Userspace should know this limitation by checking the IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 flag reported in the IOMMU_GET_HW_INFO ioctl. [1] https://www.intel.com/content/www/us/en/content-details/772415/content-details.html Link: https://lore.kernel.org/r/20231026044216.64964-9-yi.l.liu@intel.com Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -2194,6 +2194,11 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
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return -EINVAL;
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if (!(prot & DMA_PTE_WRITE) && domain->nested_parent) {
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pr_err_ratelimited("Read-only mapping is disallowed on the domain which serves as the parent in a nested configuration, due to HW errata (ERRATA_772415_SPR17)\n");
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return -EINVAL;
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}
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attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);
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attr |= DMA_FL_PTE_PRESENT;
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if (domain->use_first_level) {
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@ -4850,6 +4855,7 @@ static void *intel_iommu_hw_info(struct device *dev, u32 *length, u32 *type)
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if (!vtd)
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return ERR_PTR(-ENOMEM);
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vtd->flags = IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17;
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vtd->cap_reg = iommu->cap;
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vtd->ecap_reg = iommu->ecap;
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*length = sizeof(*vtd);
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@ -443,10 +443,20 @@ struct iommu_hwpt_alloc {
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};
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#define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC)
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/**
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* enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info
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* @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings
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* on a nested_parent domain.
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* https://www.intel.com/content/www/us/en/content-details/772415/content-details.html
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*/
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enum iommu_hw_info_vtd_flags {
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IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1 << 0,
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};
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/**
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* struct iommu_hw_info_vtd - Intel VT-d hardware information
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*
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* @flags: Must be 0
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* @flags: Combination of enum iommu_hw_info_vtd_flags
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* @__reserved: Must be 0
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*
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* @cap_reg: Value of Intel VT-d capability register defined in VT-d spec
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