mirror of
https://github.com/torvalds/linux
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staging: brcm80211: nicpci: Neatening
Remove unnecessary casts of void *. Spacing and removal of unnecessary parentheses. 80 column wrapping. Comment neatening. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Joe Perches
Greg Kroah-Hartman
parent
84db550cbd
commit
02cc343b83
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@ -38,28 +38,36 @@
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#define SRSH_BD_OFFSET 6 /* word 6 */
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/* chipcontrol */
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#define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */
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#define CHIPCTRL_4321_PLL_DOWN 0x800000/* serdes PLL down override */
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/* MDIO control */
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#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
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#define MDIOCTL_DIVISOR_VAL 0x2
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#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
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#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
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#define MDIOCTL_ACCESS_DONE 0x100 /* Transaction complete */
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/* MDIO Data */
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#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
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#define MDIODATA_TA 0x00020000 /* Turnaround */
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#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
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#define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
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#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
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#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
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#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
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#define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
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#define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
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#define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
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#define MDIODATA_WRITE 0x10000000 /* write Transaction */
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#define MDIODATA_READ 0x20000000 /* Read Transaction */
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#define MDIODATA_START 0x40000000 /* start of Transaction */
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#define MDIODATA_DEVADDR_MASK 0x0f800000
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/* Physmedia devaddr Mask */
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/* MDIO Data for older revisions < 10 */
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#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift */
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#define MDIODATA_REGADDR_MASK_OLD 0x003c0000
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/* Regaddr Mask */
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#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift */
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#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000
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/* Physmedia devaddr Mask */
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/* Transactions flags */
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#define MDIODATA_WRITE 0x10000000
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#define MDIODATA_READ 0x20000000
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#define MDIODATA_START 0x40000000
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#define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
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#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
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@ -69,21 +77,21 @@
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#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
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#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
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/* SERDES RX registers */
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/* SERDES RX registers */
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#define SERDES_RX_CTRL 1 /* Rx cntrl */
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#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
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#define SERDES_RX_CDR 6 /* CDR */
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#define SERDES_RX_CDRBW 7 /* CDR BW */
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/* SERDES RX control register */
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/* SERDES RX control register */
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#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
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#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
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/* SERDES PLL registers */
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/* SERDES PLL registers */
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#define SERDES_PLL_CTRL 1 /* PLL control reg */
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#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
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/* Linkcontrol reg offset in PCIE Cap */
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#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
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#define PCIE_CAP_LINKCTRL_OFFSET 16 /* offset in pcie cap */
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#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
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#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
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#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
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@ -97,9 +105,12 @@
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#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
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#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
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#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
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#define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
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#define PCIE_ASPMTIMER_EXTEND 0x01000000
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/* > rev7:
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* enable extend ASPM timer
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*/
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/* different register spaces to access thr'u pcie indirect access */
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/* different register spaces to access thru pcie indirect access */
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#define PCIE_CONFIGREGS 1 /* Access to config space */
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#define PCIE_PCIEREGS 2 /* Access to pcie registers */
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@ -170,7 +181,9 @@ struct sbpcieregs {
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u32 mdiodata; /* Data to the mdio access: 0x12c */
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/* pcie protocol phy/dllp/tlp register indirect access mechanism */
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u32 pcieindaddr; /* indirect access to the internal register: 0x130 */
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u32 pcieindaddr; /* indirect access to
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* the internal register: 0x130
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*/
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u32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
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u32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
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@ -187,7 +200,9 @@ struct pcicore_info {
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struct si_pub *sih; /* System interconnect handle */
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struct pci_dev *dev;
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u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
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u8 pciecap_lcreg_offset;/* PCIE capability LCreg offset
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* in the config space
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*/
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bool pcie_pr42767;
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u8 pcie_polarity;
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u8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */
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@ -199,7 +214,8 @@ struct pcicore_info {
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/* debug/trace */
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#define PCI_ERROR(args)
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#define PCIE_PUB(sih) \
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(((sih)->bustype == PCI_BUS) && ((sih)->buscoretype == PCIE_CORE_ID))
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(((sih)->bustype == PCI_BUS) && \
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((sih)->buscoretype == PCIE_CORE_ID))
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/* routines to access mdio slave device registers */
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static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk);
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@ -219,14 +235,17 @@ static void pcie_war_noplldown(struct pcicore_info *pi);
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static void pcie_war_polarity(struct pcicore_info *pi);
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static void pcie_war_pci_setup(struct pcicore_info *pi);
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#define PCIE_ASPM(sih) ((PCIE_PUB(sih)) && (((sih)->buscorerev >= 3) && ((sih)->buscorerev <= 5)))
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#define PCIE_ASPM(sih) \
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((PCIE_PUB(sih)) && \
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(((sih)->buscorerev >= 3) && \
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((sih)->buscorerev <= 5)))
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/* delay needed between the mdio control/ mdiodata register data access */
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#define PR28829_DELAY() udelay(10)
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/* Initialize the PCI core. It's caller's responsibility to make sure that this is done
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* only once
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/* Initialize the PCI core.
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* It's caller's responsibility to make sure that this is done only once
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*/
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void *pcicore_init(struct si_pub *sih, void *pdev, void *regs)
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{
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@ -244,23 +263,19 @@ void *pcicore_init(struct si_pub *sih, void *pdev, void *regs)
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if (sih->buscoretype == PCIE_CORE_ID) {
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u8 cap_ptr;
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pi->regs.pcieregs = (struct sbpcieregs *) regs;
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pi->regs.pcieregs = regs;
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cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
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NULL, NULL);
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pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
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} else
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pi->regs.pciregs = (struct sbpciregs *) regs;
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pi->regs.pciregs = regs;
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return pi;
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}
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void pcicore_deinit(void *pch)
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{
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struct pcicore_info *pi = (struct pcicore_info *) pch;
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if (pi == NULL)
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return;
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kfree(pi);
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kfree(pch);
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}
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/* return cap_offset if requested capability exists in the PCI config space */
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@ -289,7 +304,9 @@ pcicore_find_pci_capability(void *dev, u8 req_cap_id,
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if (cap_ptr == 0x00)
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goto end;
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/* loop thr'u the capability list and see if the pcie capabilty exists */
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/* loop thru the capability list
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* and see if the pcie capability exists
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*/
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pci_read_config_byte(dev, cap_ptr, &cap_id);
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@ -299,18 +316,18 @@ pcicore_find_pci_capability(void *dev, u8 req_cap_id,
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break;
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pci_read_config_byte(dev, cap_ptr, &cap_id);
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}
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if (cap_id != req_cap_id) {
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if (cap_id != req_cap_id)
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goto end;
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}
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/* found the caller requested capability */
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if ((buf != NULL) && (buflen != NULL)) {
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if (buf != NULL && buflen != NULL) {
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u8 cap_data;
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bufsize = *buflen;
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if (!bufsize)
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goto end;
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*buflen = 0;
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/* copy the cpability data excluding cap ID and next ptr */
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/* copy the capability data excluding cap ID and next ptr */
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cap_data = cap_ptr + 2;
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if ((bufsize + cap_data) > PCI_SZPCR)
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bufsize = PCI_SZPCR - cap_data;
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@ -321,29 +338,26 @@ pcicore_find_pci_capability(void *dev, u8 req_cap_id,
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buf++;
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}
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}
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end:
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end:
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return cap_ptr;
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}
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/* ***** Register Access API */
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static uint
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pcie_readreg(struct sbpcieregs *pcieregs, uint addrtype,
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uint offset)
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pcie_readreg(struct sbpcieregs *pcieregs, uint addrtype, uint offset)
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{
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uint retval = 0xFFFFFFFF;
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switch (addrtype) {
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case PCIE_CONFIGREGS:
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W_REG((&pcieregs->configaddr), offset);
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W_REG(&pcieregs->configaddr, offset);
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(void)R_REG((&pcieregs->configaddr));
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retval = R_REG(&(pcieregs->configdata));
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retval = R_REG(&pcieregs->configdata);
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break;
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case PCIE_PCIEREGS:
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W_REG(&(pcieregs->pcieindaddr), offset);
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(void)R_REG((&pcieregs->pcieindaddr));
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retval = R_REG(&(pcieregs->pcieinddata));
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break;
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default:
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W_REG(&pcieregs->pcieindaddr, offset);
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(void)R_REG(&pcieregs->pcieindaddr);
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retval = R_REG(&pcieregs->pcieinddata);
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break;
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}
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@ -351,8 +365,7 @@ pcie_readreg(struct sbpcieregs *pcieregs, uint addrtype,
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}
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static uint
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pcie_writereg(struct sbpcieregs *pcieregs, uint addrtype,
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uint offset, uint val)
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pcie_writereg(struct sbpcieregs *pcieregs, uint addrtype, uint offset, uint val)
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{
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switch (addrtype) {
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case PCIE_CONFIGREGS:
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@ -375,20 +388,17 @@ static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
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uint mdiodata, i = 0;
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uint pcie_serdes_spinwait = 200;
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mdiodata =
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MDIODATA_START | MDIODATA_WRITE | (MDIODATA_DEV_ADDR <<
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MDIODATA_DEVADDR_SHF) |
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(MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) | MDIODATA_TA | (blk <<
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4);
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mdiodata = (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
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(MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
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(MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) |
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(blk << 4));
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W_REG(&pcieregs->mdiodata, mdiodata);
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PR28829_DELAY();
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/* retry till the transaction is complete */
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while (i < pcie_serdes_spinwait) {
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if (R_REG(&(pcieregs->mdiocontrol)) &
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MDIOCTL_ACCESS_DONE) {
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if (R_REG(&pcieregs->mdiocontrol) & MDIOCTL_ACCESS_DONE)
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break;
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}
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udelay(1000);
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i++;
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}
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@ -411,26 +421,27 @@ pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
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uint pcie_serdes_spinwait = 10;
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/* enable mdio access to SERDES */
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W_REG((&pcieregs->mdiocontrol),
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MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
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W_REG(&pcieregs->mdiocontrol, MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
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if (pi->sih->buscorerev >= 10) {
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/* new serdes is slower in rw, using two layers of reg address mapping */
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/* new serdes is slower in rw,
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* using two layers of reg address mapping
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*/
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if (!pcie_mdiosetblock(pi, physmedia))
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return 1;
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mdiodata = (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
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(regaddr << MDIODATA_REGADDR_SHF);
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mdiodata = ((MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
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(regaddr << MDIODATA_REGADDR_SHF));
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pcie_serdes_spinwait *= 20;
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} else {
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mdiodata = (physmedia << MDIODATA_DEVADDR_SHF_OLD) |
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(regaddr << MDIODATA_REGADDR_SHF_OLD);
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mdiodata = ((physmedia << MDIODATA_DEVADDR_SHF_OLD) |
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(regaddr << MDIODATA_REGADDR_SHF_OLD));
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}
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if (!write)
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mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
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else
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mdiodata |=
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(MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA | *val);
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mdiodata |= (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
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*val);
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W_REG(&pcieregs->mdiodata, mdiodata);
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@ -438,16 +449,14 @@ pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
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/* retry till the transaction is complete */
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while (i < pcie_serdes_spinwait) {
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if (R_REG(&(pcieregs->mdiocontrol)) &
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MDIOCTL_ACCESS_DONE) {
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if (R_REG(&pcieregs->mdiocontrol) & MDIOCTL_ACCESS_DONE) {
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if (!write) {
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PR28829_DELAY();
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*val =
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(R_REG(&(pcieregs->mdiodata)) &
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*val = (R_REG(&pcieregs->mdiodata) &
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MDIODATA_MASK);
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}
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/* Disable mdio access to SERDES */
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W_REG((&pcieregs->mdiocontrol), 0);
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W_REG(&pcieregs->mdiocontrol, 0);
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return 0;
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}
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udelay(1000);
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@ -456,7 +465,7 @@ pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
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PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write));
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/* Disable mdio access to SERDES */
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W_REG((&pcieregs->mdiocontrol), 0);
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W_REG(&pcieregs->mdiocontrol, 0);
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return 1;
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}
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@ -478,7 +487,7 @@ pcie_mdiowrite(struct pcicore_info *pi, uint physmedia, uint regaddr, uint val)
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/* ***** Support functions ***** */
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static u8 pcie_clkreq(void *pch, u32 mask, u32 val)
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{
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struct pcicore_info *pi = (struct pcicore_info *) pch;
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struct pcicore_info *pi = pch;
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u32 reg_val;
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u8 offset;
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@ -533,8 +542,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
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case SI_PCIDOWN:
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if (sih->buscorerev == 6) { /* turn on serdes PLL down */
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ai_corereg(sih, SI_CC_IDX,
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offsetof(chipcregs_t, chipcontrol_addr), ~0,
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0);
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offsetof(chipcregs_t, chipcontrol_addr),
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~0, 0);
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ai_corereg(sih, SI_CC_IDX,
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offsetof(chipcregs_t, chipcontrol_data),
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~0x40, 0);
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@ -545,8 +554,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
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case SI_PCIUP:
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if (sih->buscorerev == 6) { /* turn off serdes PLL down */
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ai_corereg(sih, SI_CC_IDX,
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offsetof(chipcregs_t, chipcontrol_addr), ~0,
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0);
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offsetof(chipcregs_t, chipcontrol_addr),
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~0, 0);
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ai_corereg(sih, SI_CC_IDX,
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offsetof(chipcregs_t, chipcontrol_data),
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~0x40, 0x40);
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@ -554,8 +563,6 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
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pcie_clkreq((void *)pi, 1, 0);
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}
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break;
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default:
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break;
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}
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}
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@ -568,17 +575,16 @@ static void pcie_war_polarity(struct pcicore_info *pi)
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if (pi->pcie_polarity != 0)
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return;
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w = pcie_readreg(pi->regs.pcieregs, PCIE_PCIEREGS,
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PCIE_PLP_STATUSREG);
|
||||
w = pcie_readreg(pi->regs.pcieregs, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
|
||||
|
||||
/* Detect the current polarity at attach and force that polarity and
|
||||
* disable changing the polarity
|
||||
*/
|
||||
if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
|
||||
pi->pcie_polarity = (SERDES_RX_CTRL_FORCE);
|
||||
pi->pcie_polarity = SERDES_RX_CTRL_FORCE;
|
||||
else
|
||||
pi->pcie_polarity =
|
||||
(SERDES_RX_CTRL_FORCE | SERDES_RX_CTRL_POLARITY);
|
||||
pi->pcie_polarity = (SERDES_RX_CTRL_FORCE |
|
||||
SERDES_RX_CTRL_POLARITY);
|
||||
}
|
||||
|
||||
/* enable ASPM and CLKREQ if srom doesn't have it */
|
||||
|
|
@ -683,7 +689,7 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
|
|||
struct sbpcieregs *pcieregs = pi->regs.pcieregs;
|
||||
u32 w;
|
||||
|
||||
if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
|
||||
if (sih->buscorerev == 0 || sih->buscorerev == 1) {
|
||||
w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
|
||||
PCIE_TLP_WORKAROUNDSREG);
|
||||
w |= 0x8;
|
||||
|
|
@ -693,7 +699,7 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
|
|||
|
||||
if (sih->buscorerev == 1) {
|
||||
w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
|
||||
w |= (0x40);
|
||||
w |= 0x40;
|
||||
pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
|
||||
}
|
||||
|
||||
|
|
@ -705,8 +711,8 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
|
|||
/* Change the L1 threshold for better performance */
|
||||
w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
|
||||
PCIE_DLLP_PMTHRESHREG);
|
||||
w &= ~(PCIE_L1THRESHOLDTIME_MASK);
|
||||
w |= (PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT);
|
||||
w &= ~PCIE_L1THRESHOLDTIME_MASK;
|
||||
w |= PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT;
|
||||
pcie_writereg(pcieregs, PCIE_PCIEREGS,
|
||||
PCIE_DLLP_PMTHRESHREG, w);
|
||||
|
||||
|
|
@ -716,7 +722,9 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
|
|||
} else if (pi->sih->buscorerev == 7)
|
||||
pcie_war_noplldown(pi);
|
||||
|
||||
/* Note that the fix is actually in the SROM, that's why this is open-ended */
|
||||
/* Note that the fix is actually in the SROM,
|
||||
* that's why this is open-ended
|
||||
*/
|
||||
if (pi->sih->buscorerev >= 6)
|
||||
pcie_misc_config_fixup(pi);
|
||||
}
|
||||
|
|
@ -724,17 +732,16 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
|
|||
/* ***** Functions called during driver state changes ***** */
|
||||
void pcicore_attach(void *pch, char *pvars, int state)
|
||||
{
|
||||
struct pcicore_info *pi = (struct pcicore_info *) pch;
|
||||
struct pcicore_info *pi = pch;
|
||||
struct si_pub *sih = pi->sih;
|
||||
|
||||
/* Determine if this board needs override */
|
||||
if (PCIE_ASPM(sih)) {
|
||||
if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
|
||||
if ((u32)getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR)
|
||||
pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
|
||||
} else {
|
||||
else
|
||||
pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
|
||||
}
|
||||
}
|
||||
|
||||
/* These need to happen in this order only */
|
||||
pcie_war_polarity(pi);
|
||||
|
|
@ -749,7 +756,7 @@ void pcicore_attach(void *pch, char *pvars, int state)
|
|||
|
||||
void pcicore_hwup(void *pch)
|
||||
{
|
||||
struct pcicore_info *pi = (struct pcicore_info *) pch;
|
||||
struct pcicore_info *pi = pch;
|
||||
|
||||
if (!pi || !PCIE_PUB(pi->sih))
|
||||
return;
|
||||
|
|
@ -759,7 +766,7 @@ void pcicore_hwup(void *pch)
|
|||
|
||||
void pcicore_up(void *pch, int state)
|
||||
{
|
||||
struct pcicore_info *pi = (struct pcicore_info *) pch;
|
||||
struct pcicore_info *pi = pch;
|
||||
|
||||
if (!pi || !PCIE_PUB(pi->sih))
|
||||
return;
|
||||
|
|
@ -770,10 +777,12 @@ void pcicore_up(void *pch, int state)
|
|||
pcie_clkreq_upd(pi, state);
|
||||
}
|
||||
|
||||
/* When the device is going to enter D3 state (or the system is going to enter S3/S4 states */
|
||||
/* When the device is going to enter D3 state
|
||||
* (or the system is going to enter S3/S4 states)
|
||||
*/
|
||||
void pcicore_sleep(void *pch)
|
||||
{
|
||||
struct pcicore_info *pi = (struct pcicore_info *) pch;
|
||||
struct pcicore_info *pi = pch;
|
||||
u32 w;
|
||||
|
||||
if (!pi || !PCIE_ASPM(pi->sih))
|
||||
|
|
@ -788,7 +797,7 @@ void pcicore_sleep(void *pch)
|
|||
|
||||
void pcicore_down(void *pch, int state)
|
||||
{
|
||||
struct pcicore_info *pi = (struct pcicore_info *) pch;
|
||||
struct pcicore_info *pi = pch;
|
||||
|
||||
if (!pi || !PCIE_PUB(pi->sih))
|
||||
return;
|
||||
|
|
@ -799,12 +808,10 @@ void pcicore_down(void *pch, int state)
|
|||
pcie_extendL1timer(pi, false);
|
||||
}
|
||||
|
||||
/*
|
||||
* precondition: current core is sii->buscoretype
|
||||
*/
|
||||
/* precondition: current core is sii->buscoretype */
|
||||
void pcicore_fixcfg(void *pch, void *regs)
|
||||
{
|
||||
struct pcicore_info *pi = (struct pcicore_info *) pch;
|
||||
struct pcicore_info *pi = pch;
|
||||
struct si_info *sii = SI_INFO(pi->sih);
|
||||
struct sbpciregs *pciregs = regs;
|
||||
struct sbpcieregs *pcieregs = regs;
|
||||
|
|
@ -812,39 +819,32 @@ void pcicore_fixcfg(void *pch, void *regs)
|
|||
uint pciidx;
|
||||
|
||||
/* check 'pi' is correct and fix it if not */
|
||||
if (sii->pub.buscoretype == PCIE_CORE_ID) {
|
||||
if (sii->pub.buscoretype == PCIE_CORE_ID)
|
||||
reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
|
||||
} else if (sii->pub.buscoretype == PCI_CORE_ID) {
|
||||
else if (sii->pub.buscoretype == PCI_CORE_ID)
|
||||
reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
|
||||
}
|
||||
pciidx = ai_coreidx(&sii->pub);
|
||||
val16 = R_REG(reg16);
|
||||
if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
|
||||
val16 =
|
||||
(u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
|
||||
~SRSH_PI_MASK);
|
||||
if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16)pciidx) {
|
||||
val16 = (u16)(pciidx << SRSH_PI_SHIFT) |
|
||||
(val16 & ~SRSH_PI_MASK);
|
||||
W_REG(reg16, val16);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* precondition: current core is pci core
|
||||
*/
|
||||
/* precondition: current core is pci core */
|
||||
void pcicore_pci_setup(void *pch, void *regs)
|
||||
{
|
||||
struct pcicore_info *pi = (struct pcicore_info *) pch;
|
||||
struct pcicore_info *pi = pch;
|
||||
struct sbpciregs *pciregs = regs;
|
||||
u32 w;
|
||||
|
||||
OR_REG(&pciregs->sbtopci2,
|
||||
(SBTOPCI_PREF | SBTOPCI_BURST));
|
||||
OR_REG(&pciregs->sbtopci2, SBTOPCI_PREF | SBTOPCI_BURST);
|
||||
|
||||
if (SI_INFO(pi->sih)->pub.buscorerev >= 11) {
|
||||
OR_REG(&pciregs->sbtopci2,
|
||||
SBTOPCI_RC_READMULTI);
|
||||
OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
|
||||
w = R_REG(&pciregs->clkrun);
|
||||
W_REG(&pciregs->clkrun,
|
||||
(w | PCI_CLKRUN_DSBL));
|
||||
W_REG(&pciregs->clkrun, w | PCI_CLKRUN_DSBL);
|
||||
w = R_REG(&pciregs->clkrun);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue