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phy: qcom: qmp-combo: fix VCO div offset on v5_5nm and v6
Commit5abed58a8b
("phy: qcom: qmp-combo: Fix VCO div offset on v3") fixed a regression introduced in 6.5 by making sure that the correct offset is used for the DP_PHY_VCO_DIV register on v3 hardware. Unfortunately, that fix instead broke DisplayPort on v5_5nm and v6 hardware as it failed to add the corresponding offsets also to those register tables. Fixes:815891eee6
("phy: qcom-qmp-combo: Introduce orientation variable") Fixes:5abed58a8b
("phy: qcom: qmp-combo: Fix VCO div offset on v3") Cc: stable@vger.kernel.org # 6.5:5abed58a8b
Cc: Stephen Boyd <swboyd@chromium.org> Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20240408093023.506-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -153,6 +153,7 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN,
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[QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS,
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[QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV,
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[QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV,
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[QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL,
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@ -177,6 +178,7 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
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[QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
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[QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV,
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[QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV,
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[QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL,
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@ -7,6 +7,7 @@
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#define QCOM_PHY_QMP_DP_PHY_V5_H_
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/* Only for QMP V5 PHY - DP PHY registers */
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#define QSERDES_V5_DP_PHY_VCO_DIV 0x070
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#define QSERDES_V5_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
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#define QSERDES_V5_DP_PHY_STATUS 0x0dc
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@ -7,6 +7,7 @@
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#define QCOM_PHY_QMP_DP_PHY_V6_H_
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/* Only for QMP V6 PHY - DP PHY registers */
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#define QSERDES_V6_DP_PHY_VCO_DIV 0x070
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#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
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#define QSERDES_V6_DP_PHY_STATUS 0x0e4
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