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drm/bridge: analogix-anx78xx: add support for 7808 addresses

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According to the downstream Android sources, the anx7808 variants use
address 0x78 for TX_P0 and the anx781x variants use address 0x70. Since
the datasheets aren't available for these devices, and we only have the
downstream kernel sources to look at, let's assume that these addresses
are fixed based on the model, and pass the i2c addresses to the driver
via the data pointer in the driver's of_match_table.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190922175940.5311-1-masneyb@onstation.org
This commit is contained in:
Brian Masney 2019-09-22 13:59:40 -04:00 committed by Andrzej Hajda
parent 710abfe8ea
commit 025910db80
2 changed files with 28 additions and 25 deletions
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36
drivers/gpu/drm/bridge/analogix-anx78xx.c
View file

@ -39,12 +39,20 @@
#define AUX_CH_BUFFER_SIZE 16
#define AUX_WAIT_TIMEOUT_MS 15
static const u8 anx78xx_i2c_addresses[] = {
[I2C_IDX_TX_P0] = TX_P0,
[I2C_IDX_TX_P1] = TX_P1,
[I2C_IDX_TX_P2] = TX_P2,
[I2C_IDX_RX_P0] = RX_P0,
[I2C_IDX_RX_P1] = RX_P1,
static const u8 anx7808_i2c_addresses[] = {
[I2C_IDX_TX_P0] = 0x78,
[I2C_IDX_TX_P1] = 0x7a,
[I2C_IDX_TX_P2] = 0x72,
[I2C_IDX_RX_P0] = 0x7e,
[I2C_IDX_RX_P1] = 0x80,
};
static const u8 anx781x_i2c_addresses[] = {
[I2C_IDX_TX_P0] = 0x70,
[I2C_IDX_TX_P1] = 0x7a,
[I2C_IDX_TX_P2] = 0x72,
[I2C_IDX_RX_P0] = 0x7e,
[I2C_IDX_RX_P1] = 0x80,
};
struct anx78xx_platform_data {
@ -1316,6 +1324,7 @@ static int anx78xx_i2c_probe(struct i2c_client *client,
struct anx78xx *anx78xx;
struct anx78xx_platform_data *pdata;
unsigned int i, idl, idh, version;
const u8 *i2c_addresses;
bool found = false;
int err;
@ -1355,15 +1364,16 @@ static int anx78xx_i2c_probe(struct i2c_client *client,
}
/* Map slave addresses of ANX7814 */
i2c_addresses = device_get_match_data(&client->dev);
for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
struct i2c_client *i2c_dummy;
i2c_dummy = i2c_new_dummy_device(client->adapter,
anx78xx_i2c_addresses[i] >> 1);
i2c_addresses[i] >> 1);
if (IS_ERR(i2c_dummy)) {
err = PTR_ERR(i2c_dummy);
DRM_ERROR("Failed to reserve I2C bus %02x: %d\n",
anx78xx_i2c_addresses[i], err);
i2c_addresses[i], err);
goto err_unregister_i2c;
}
@ -1373,7 +1383,7 @@ static int anx78xx_i2c_probe(struct i2c_client *client,
if (IS_ERR(anx78xx->map[i])) {
err = PTR_ERR(anx78xx->map[i]);
DRM_ERROR("Failed regmap initialization %02x\n",
anx78xx_i2c_addresses[i]);
i2c_addresses[i]);
goto err_unregister_i2c;
}
}
@ -1472,10 +1482,10 @@ MODULE_DEVICE_TABLE(i2c, anx78xx_id);
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id anx78xx_match_table[] = {
{ .compatible = "analogix,anx7808", },
{ .compatible = "analogix,anx7812", },
{ .compatible = "analogix,anx7814", },
{ .compatible = "analogix,anx7818", },
{ .compatible = "analogix,anx7808", .data = anx7808_i2c_addresses },
{ .compatible = "analogix,anx7812", .data = anx781x_i2c_addresses },
{ .compatible = "analogix,anx7814", .data = anx781x_i2c_addresses },
{ .compatible = "analogix,anx7818", .data = anx781x_i2c_addresses },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, anx78xx_match_table);

17
drivers/gpu/drm/bridge/analogix-anx78xx.h
View file

@ -6,15 +6,8 @@
#ifndef __ANX78xx_H
#define __ANX78xx_H
#define TX_P0 0x70
#define TX_P1 0x7a
#define TX_P2 0x72
#define RX_P0 0x7e
#define RX_P1 0x80
/***************************************************************/
/* Register definition of device address 0x7e */
/* Register definitions for RX_PO */
/***************************************************************/
/*
@ -171,7 +164,7 @@
#define SP_VSI_RCVD BIT(1)
/***************************************************************/
/* Register definition of device address 0x80 */
/* Register definitions for RX_P1 */
/***************************************************************/
/* HDCP BCAPS Shadow Register */
@ -217,7 +210,7 @@
#define SP_SET_AVMUTE BIT(0)
/***************************************************************/
/* Register definition of device address 0x70 */
/* Register definitions for TX_P0 */
/***************************************************************/
/* HDCP Status Register */
@ -451,7 +444,7 @@
#define SP_DP_BUF_DATA0_REG 0xf0
/***************************************************************/
/* Register definition of device address 0x72 */
/* Register definitions for TX_P2 */
/***************************************************************/
/*
@ -674,7 +667,7 @@
#define SP_INT_CTRL_REG 0xff
/***************************************************************/
/* Register definition of device address 0x7a */
/* Register definitions for TX_P1 */
/***************************************************************/
/* DP TX Link Training Control Register */