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habanalabs: Unify frequency set/get functionality
Make the frequency set/get functionality common to all ASICs. This makes more code reusable when adding support for newer ASICs. Signed-off-by: Rajaravi Krishna Katta <rkatta@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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@ -11,4 +11,4 @@ HL_COMMON_FILES := common/habanalabs_drv.o common/device.o common/context.o \
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common/command_buffer.o common/hw_queue.o common/irq.o \
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common/sysfs.o common/hwmon.o common/memory.o \
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common/command_submission.o common/firmware_if.o \
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common/state_dump.o
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common/state_dump.o common/hwmgr.o
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@ -456,6 +456,9 @@ struct hl_hints_range {
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* for hints validity check.
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* device_dma_offset_for_host_access: the offset to add to host DMA addresses
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* to enable the device to access them.
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* @max_freq_value: current max clk frequency.
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* @clk_pll_index: clock PLL index that specify which PLL determines the clock
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* we display to the user
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* @mmu_pgt_size: MMU page tables total size.
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* @mmu_pte_size: PTE size in MMU page tables.
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* @mmu_hop_table_size: MMU hop table size.
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@ -552,6 +555,8 @@ struct asic_fixed_properties {
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u64 cb_va_end_addr;
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u64 dram_hints_align_mask;
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u64 device_dma_offset_for_host_access;
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u64 max_freq_value;
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u32 clk_pll_index;
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u32 mmu_pgt_size;
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u32 mmu_pte_size;
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u32 mmu_hop_table_size;
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@ -3006,6 +3011,11 @@ int hl_set_power(struct hl_device *hdev,
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int sensor_index, u32 attr, long value);
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int hl_get_power(struct hl_device *hdev,
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int sensor_index, u32 attr, long *value);
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int hl_get_clk_rate(struct hl_device *hdev,
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u32 *cur_clk, u32 *max_clk);
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void hl_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
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void hl_add_device_attr(struct hl_device *hdev,
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struct attribute_group *dev_attr_grp);
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void hw_sob_get(struct hl_hw_sob *hw_sob);
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void hw_sob_put(struct hl_hw_sob *hw_sob);
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void hl_encaps_handle_do_release(struct kref *ref);
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@ -1,29 +1,26 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* Copyright 2019-2021 HabanaLabs, Ltd.
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* All Rights Reserved.
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*/
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#include "gaudiP.h"
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#include "../include/gaudi/gaudi_fw_if.h"
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#include "habanalabs.h"
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void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq)
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void hl_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq)
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{
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struct gaudi_device *gaudi = hdev->asic_specific;
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if (freq == PLL_LAST)
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hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);
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hl_set_frequency(hdev, hdev->asic_prop.clk_pll_index,
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hdev->asic_prop.max_freq_value);
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}
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int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)
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int hl_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)
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{
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long value;
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if (!hl_device_operational(hdev, NULL))
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return -ENODEV;
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value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);
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value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, false);
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if (value < 0) {
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dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",
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@ -33,7 +30,7 @@ int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)
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*max_clk = (value / 1000 / 1000);
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value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);
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value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, true);
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if (value < 0) {
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dev_err(hdev->dev,
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@ -51,15 +48,14 @@ static ssize_t clk_max_freq_mhz_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct hl_device *hdev = dev_get_drvdata(dev);
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struct gaudi_device *gaudi = hdev->asic_specific;
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long value;
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if (!hl_device_operational(hdev, NULL))
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return -ENODEV;
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value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);
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value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, false);
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gaudi->max_freq_value = value;
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hdev->asic_prop.max_freq_value = value;
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return sprintf(buf, "%lu\n", (value / 1000 / 1000));
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}
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@ -68,7 +64,6 @@ static ssize_t clk_max_freq_mhz_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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struct hl_device *hdev = dev_get_drvdata(dev);
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struct gaudi_device *gaudi = hdev->asic_specific;
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int rc;
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u64 value;
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@ -83,9 +78,10 @@ static ssize_t clk_max_freq_mhz_store(struct device *dev,
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goto fail;
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}
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gaudi->max_freq_value = value * 1000 * 1000;
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hdev->asic_prop.max_freq_value = value * 1000 * 1000;
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hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);
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hl_set_frequency(hdev, hdev->asic_prop.clk_pll_index,
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hdev->asic_prop.max_freq_value);
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fail:
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return count;
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@ -100,7 +96,7 @@ static ssize_t clk_cur_freq_mhz_show(struct device *dev,
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if (!hl_device_operational(hdev, NULL))
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return -ENODEV;
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value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);
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value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, true);
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return sprintf(buf, "%lu\n", (value / 1000 / 1000));
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}
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@ -108,14 +104,14 @@ static ssize_t clk_cur_freq_mhz_show(struct device *dev,
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static DEVICE_ATTR_RW(clk_max_freq_mhz);
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static DEVICE_ATTR_RO(clk_cur_freq_mhz);
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static struct attribute *gaudi_dev_attrs[] = {
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static struct attribute *hl_dev_attrs[] = {
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&dev_attr_clk_max_freq_mhz.attr,
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&dev_attr_clk_cur_freq_mhz.attr,
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NULL,
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};
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void gaudi_add_device_attr(struct hl_device *hdev,
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void hl_add_device_attr(struct hl_device *hdev,
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struct attribute_group *dev_attr_grp)
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{
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dev_attr_grp->attrs = gaudi_dev_attrs;
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dev_attr_grp->attrs = hl_dev_attrs;
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}
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@ -1,3 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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HL_GAUDI_FILES := gaudi/gaudi.o gaudi/gaudi_hwmgr.o gaudi/gaudi_security.o \
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HL_GAUDI_FILES := gaudi/gaudi.o gaudi/gaudi_security.o \
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gaudi/gaudi_coresight.o
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@ -661,6 +661,9 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev)
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prop->server_type = HL_SERVER_TYPE_UNKNOWN;
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prop->clk_pll_index = HL_GAUDI_MME_PLL;
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prop->max_freq_value = GAUDI_MAX_CLK_FREQ;
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return 0;
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}
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@ -1838,8 +1841,6 @@ static int gaudi_sw_init(struct hl_device *hdev)
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gaudi->cpucp_info_get = gaudi_cpucp_info_get;
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gaudi->max_freq_value = GAUDI_MAX_CLK_FREQ;
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hdev->asic_specific = gaudi;
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/* Create DMA pool for small allocations */
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@ -9444,9 +9445,9 @@ static const struct hl_asic_funcs gaudi_funcs = {
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.debugfs_read64 = gaudi_debugfs_read64,
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.debugfs_write64 = gaudi_debugfs_write64,
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.debugfs_read_dma = gaudi_debugfs_read_dma,
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.add_device_attr = gaudi_add_device_attr,
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.add_device_attr = hl_add_device_attr,
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.handle_eqe = gaudi_handle_eqe,
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.set_pll_profile = gaudi_set_pll_profile,
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.set_pll_profile = hl_set_pll_profile,
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.get_events_stat = gaudi_get_events_stat,
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.read_pte = gaudi_read_pte,
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.write_pte = gaudi_write_pte,
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@ -9470,7 +9471,7 @@ static const struct hl_asic_funcs gaudi_funcs = {
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.halt_coresight = gaudi_halt_coresight,
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.ctx_init = gaudi_ctx_init,
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.ctx_fini = gaudi_ctx_fini,
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.get_clk_rate = gaudi_get_clk_rate,
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.get_clk_rate = hl_get_clk_rate,
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.get_queue_id_for_cq = gaudi_get_queue_id_for_cq,
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.load_firmware_to_device = gaudi_load_firmware_to_device,
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.load_boot_fit_to_device = gaudi_load_boot_fit_to_device,
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@ -319,7 +319,6 @@ struct gaudi_internal_qman_info {
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* the actual number of internal queues because they are not in
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* consecutive order.
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* @hbm_bar_cur_addr: current address of HBM PCI bar.
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* @max_freq_value: current max clk frequency.
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* @events: array that holds all event id's
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* @events_stat: array that holds histogram of all received events.
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* @events_stat_aggregate: same as events_stat but doesn't get cleared on reset
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@ -345,7 +344,6 @@ struct gaudi_device {
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struct gaudi_collective_properties collective_props;
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u64 hbm_bar_cur_addr;
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u64 max_freq_value;
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u32 events[GAUDI_EVENT_SIZE];
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u32 events_stat[GAUDI_EVENT_SIZE];
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@ -359,10 +357,8 @@ void gaudi_init_security(struct hl_device *hdev);
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void gaudi_ack_protection_bits_errors(struct hl_device *hdev);
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void gaudi_add_device_attr(struct hl_device *hdev,
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struct attribute_group *dev_attr_grp);
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void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
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int gaudi_debug_coresight(struct hl_device *hdev, void *data);
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void gaudi_halt_coresight(struct hl_device *hdev);
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int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
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void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);
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#endif /* GAUDIP_H_ */
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@ -471,6 +471,8 @@ int goya_set_fixed_properties(struct hl_device *hdev)
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prop->server_type = HL_SERVER_TYPE_UNKNOWN;
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prop->clk_pll_index = HL_GOYA_MME_PLL;
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return 0;
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}
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@ -5656,7 +5658,7 @@ static const struct hl_asic_funcs goya_funcs = {
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.halt_coresight = goya_halt_coresight,
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.ctx_init = goya_ctx_init,
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.ctx_fini = goya_ctx_fini,
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.get_clk_rate = goya_get_clk_rate,
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.get_clk_rate = hl_get_clk_rate,
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.get_queue_id_for_cq = goya_get_queue_id_for_cq,
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.load_firmware_to_device = goya_load_firmware_to_device,
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.load_boot_fit_to_device = goya_load_boot_fit_to_device,
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@ -235,7 +235,6 @@ void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
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void *vaddr);
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void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
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int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
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u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx);
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u64 goya_get_device_time(struct hl_device *hdev);
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@ -32,37 +32,6 @@ void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq)
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}
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}
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int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)
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{
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long value;
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if (!hl_device_operational(hdev, NULL))
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return -ENODEV;
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value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, false);
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if (value < 0) {
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dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",
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value);
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return value;
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}
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*max_clk = (value / 1000 / 1000);
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value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, true);
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if (value < 0) {
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dev_err(hdev->dev,
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"Failed to retrieve device current clock %ld\n",
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value);
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return value;
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}
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*cur_clk = (value / 1000 / 1000);
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return 0;
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}
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static ssize_t mme_clk_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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