2007-06-12 16:30:17 +00:00
|
|
|
config PPC64
|
|
|
|
|
bool "64-bit kernel"
|
|
|
|
|
default n
|
2015-02-05 19:36:04 +00:00
|
|
|
select ZLIB_DEFLATE
|
2007-06-12 16:30:17 +00:00
|
|
|
help
|
|
|
|
|
This option selects whether a 32-bit or a 64-bit kernel
|
|
|
|
|
will be built.
|
|
|
|
|
|
|
|
|
|
menu "Processor support"
|
|
|
|
|
choice
|
|
|
|
|
prompt "Processor Type"
|
|
|
|
|
depends on PPC32
|
|
|
|
|
help
|
2007-06-17 23:06:52 +00:00
|
|
|
There are five families of 32 bit PowerPC chips supported.
|
|
|
|
|
The most common ones are the desktop and server CPUs (601, 603,
|
|
|
|
|
604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
|
2008-01-28 17:28:53 +00:00
|
|
|
embedded 512x/52xx/82xx/83xx/86xx counterparts.
|
2015-03-18 16:29:13 +00:00
|
|
|
The other embedded parts, namely 4xx, 8xx, e200 (55xx) and e500
|
2007-06-17 23:06:52 +00:00
|
|
|
(85xx) each form a family of their own that is not compatible
|
|
|
|
|
with the others.
|
|
|
|
|
|
|
|
|
|
If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
|
|
|
|
|
|
2009-06-14 14:45:50 +00:00
|
|
|
config PPC_BOOK3S_32
|
2008-01-28 17:28:53 +00:00
|
|
|
bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
|
2007-06-12 16:30:17 +00:00
|
|
|
select PPC_FPU
|
|
|
|
|
|
|
|
|
|
config PPC_85xx
|
|
|
|
|
bool "Freescale 85xx"
|
|
|
|
|
select E500
|
|
|
|
|
|
|
|
|
|
config PPC_8xx
|
|
|
|
|
bool "Freescale 8xx"
|
|
|
|
|
select FSL_SOC
|
2007-09-16 10:53:25 +00:00
|
|
|
select PPC_LIB_RHEAP
|
2016-12-07 07:47:28 +00:00
|
|
|
select SYS_SUPPORTS_HUGETLBFS
|
2007-06-12 16:30:17 +00:00
|
|
|
|
|
|
|
|
config 40x
|
|
|
|
|
bool "AMCC 40x"
|
|
|
|
|
select PPC_DCR_NATIVE
|
2007-12-21 04:39:26 +00:00
|
|
|
select PPC_UDBG_16550
|
2008-03-27 14:43:31 +00:00
|
|
|
select 4xx_SOC
|
2008-06-26 17:07:56 +00:00
|
|
|
select PPC_PCI_CHOICE
|
2007-06-12 16:30:17 +00:00
|
|
|
|
|
|
|
|
config 44x
|
2010-03-05 10:43:12 +00:00
|
|
|
bool "AMCC 44x, 46x or 47x"
|
2007-06-12 16:30:17 +00:00
|
|
|
select PPC_DCR_NATIVE
|
2007-10-18 12:55:13 +00:00
|
|
|
select PPC_UDBG_16550
|
2008-03-27 14:43:31 +00:00
|
|
|
select 4xx_SOC
|
2008-06-26 17:07:56 +00:00
|
|
|
select PPC_PCI_CHOICE
|
2008-09-24 16:01:24 +00:00
|
|
|
select PHYS_64BIT
|
2007-06-12 16:30:17 +00:00
|
|
|
|
|
|
|
|
config E200
|
|
|
|
|
bool "Freescale e200"
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
choice
|
|
|
|
|
prompt "Processor Type"
|
2009-06-02 21:17:37 +00:00
|
|
|
depends on PPC64
|
2009-07-23 23:15:59 +00:00
|
|
|
help
|
|
|
|
|
There are two families of 64 bit PowerPC chips supported.
|
|
|
|
|
The most common ones are the desktop and server CPUs
|
2014-07-10 02:29:24 +00:00
|
|
|
(POWER4, POWER5, 970, POWER5+, POWER6, POWER7, POWER8 ...)
|
2009-07-23 23:15:59 +00:00
|
|
|
|
|
|
|
|
The other are the "embedded" processors compliant with the
|
|
|
|
|
"Book 3E" variant of the architecture
|
|
|
|
|
|
|
|
|
|
config PPC_BOOK3S_64
|
|
|
|
|
bool "Server processors"
|
2009-06-02 21:17:37 +00:00
|
|
|
select PPC_FPU
|
2011-07-13 05:00:41 +00:00
|
|
|
select PPC_HAVE_PMU_SUPPORT
|
2011-06-28 09:54:48 +00:00
|
|
|
select SYS_SUPPORTS_HUGETLBFS
|
2016-04-29 13:26:31 +00:00
|
|
|
select HAVE_ARCH_TRANSPARENT_HUGEPAGE
|
2013-11-18 09:28:13 +00:00
|
|
|
select ARCH_SUPPORTS_NUMA_BALANCING
|
2014-04-07 22:39:08 +00:00
|
|
|
select IRQ_WORK
|
2016-09-22 06:54:34 +00:00
|
|
|
select HAVE_KERNEL_XZ
|
2009-06-02 21:17:37 +00:00
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
config PPC_BOOK3E_64
|
|
|
|
|
bool "Embedded processors"
|
|
|
|
|
select PPC_FPU # Make it a choice ?
|
2011-05-10 19:29:42 +00:00
|
|
|
select PPC_SMP_MUXED_IPI
|
2012-11-14 18:49:49 +00:00
|
|
|
select PPC_DOORBELL
|
2009-07-23 23:15:59 +00:00
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2012-04-17 18:45:28 +00:00
|
|
|
choice
|
|
|
|
|
prompt "CPU selection"
|
|
|
|
|
depends on PPC64
|
2016-09-25 12:35:41 +00:00
|
|
|
default POWER8_CPU if CPU_LITTLE_ENDIAN
|
2012-04-17 18:45:28 +00:00
|
|
|
default GENERIC_CPU
|
|
|
|
|
help
|
|
|
|
|
This will create a kernel which is optimised for a particular CPU.
|
|
|
|
|
The resulting kernel may not run on other CPUs, so use this with care.
|
|
|
|
|
|
|
|
|
|
If unsure, select Generic.
|
|
|
|
|
|
|
|
|
|
config GENERIC_CPU
|
|
|
|
|
bool "Generic"
|
2013-10-22 00:05:25 +00:00
|
|
|
depends on !CPU_LITTLE_ENDIAN
|
2012-04-17 18:45:28 +00:00
|
|
|
|
|
|
|
|
config CELL_CPU
|
|
|
|
|
bool "Cell Broadband Engine"
|
2013-10-22 00:05:25 +00:00
|
|
|
depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
|
2012-04-17 18:45:28 +00:00
|
|
|
|
|
|
|
|
config POWER4_CPU
|
|
|
|
|
bool "POWER4"
|
2013-10-22 00:05:25 +00:00
|
|
|
depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
|
2012-04-17 18:45:28 +00:00
|
|
|
|
|
|
|
|
config POWER5_CPU
|
|
|
|
|
bool "POWER5"
|
2013-10-22 00:05:25 +00:00
|
|
|
depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
|
2012-04-17 18:45:28 +00:00
|
|
|
|
|
|
|
|
config POWER6_CPU
|
|
|
|
|
bool "POWER6"
|
2013-10-22 00:05:25 +00:00
|
|
|
depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
|
2012-04-17 18:45:28 +00:00
|
|
|
|
|
|
|
|
config POWER7_CPU
|
|
|
|
|
bool "POWER7"
|
2013-08-21 00:55:36 +00:00
|
|
|
depends on PPC_BOOK3S_64
|
2014-09-16 00:49:14 +00:00
|
|
|
select ARCH_HAS_FAST_MULTIPLIER
|
2013-08-21 00:55:36 +00:00
|
|
|
|
2014-09-16 00:47:49 +00:00
|
|
|
config POWER8_CPU
|
|
|
|
|
bool "POWER8"
|
|
|
|
|
depends on PPC_BOOK3S_64
|
2014-09-16 00:49:14 +00:00
|
|
|
select ARCH_HAS_FAST_MULTIPLIER
|
2013-08-21 00:55:36 +00:00
|
|
|
|
|
|
|
|
config E5500_CPU
|
|
|
|
|
bool "Freescale e5500"
|
|
|
|
|
depends on E500
|
|
|
|
|
|
|
|
|
|
config E6500_CPU
|
|
|
|
|
bool "Freescale e6500"
|
|
|
|
|
depends on E500
|
2012-04-17 18:45:28 +00:00
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2009-06-14 14:45:50 +00:00
|
|
|
config PPC_BOOK3S
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
|
2009-03-10 17:53:27 +00:00
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
config PPC_BOOK3E
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on PPC_BOOK3E_64
|
|
|
|
|
|
2009-06-02 21:17:37 +00:00
|
|
|
config 6xx
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on PPC32 && PPC_BOOK3S
|
perf_counter: powerpc: Add processor back-end for MPC7450 family
This adds support for the performance monitor hardware on the
MPC7450 family of processors (7450, 7451, 7455, 7447/7457, 7447A,
7448), used in the later Apple G4 powermacs/powerbooks and other
machines. These machines have 6 hardware counters with a unique
set of events which can be counted on each counter, with some
events being available on multiple counters.
Raw event codes for these processors are (PMC << 8) + PMCSEL.
If PMC is non-zero then the event is that selected by the given
PMCSEL value for that PMC (hardware counter). If PMC is zero
then the event selected is one of the low-numbered ones that are
common to several PMCs. In this case PMCSEL must be <= 22 and
the event is what that PMCSEL value would select on PMC1 (but
it may be placed any other PMC that has the same event for that
PMCSEL value).
For events that count cycles or occurrences that exceed a threshold,
the threshold requested can be specified in the 0x3f000 bits of the
raw event codes. If the event uses the threshold multiplier bit
and that bit should be set, that is indicated with the 0x40000 bit
of the raw event code.
This fills in some of the generic cache events. Unfortunately there
are quite a few blank spaces in the table, partly because these
processors tend to count cache hits rather than cache accesses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: linuxppc-dev@ozlabs.org
Cc: benh@kernel.crashing.org
LKML-Reference: <19000.55631.802122.696927@cargo.ozlabs.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-17 11:53:51 +00:00
|
|
|
select PPC_HAVE_PMU_SUPPORT
|
2009-06-02 21:17:37 +00:00
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
config E500
|
2008-02-05 00:27:55 +00:00
|
|
|
select FSL_EMB_PERFMON
|
2010-10-08 13:32:11 +00:00
|
|
|
select PPC_FSL_BOOK3E
|
2007-06-12 16:30:17 +00:00
|
|
|
bool
|
|
|
|
|
|
2008-06-16 14:41:32 +00:00
|
|
|
config PPC_E500MC
|
|
|
|
|
bool "e500mc Support"
|
|
|
|
|
select PPC_FPU
|
2013-04-09 08:46:26 +00:00
|
|
|
select COMMON_CLK
|
2008-06-16 14:41:32 +00:00
|
|
|
depends on E500
|
2012-07-11 00:26:48 +00:00
|
|
|
help
|
|
|
|
|
This must be enabled for running on e500mc (and derivatives
|
|
|
|
|
such as e5500/e6500), and must be disabled for running on
|
|
|
|
|
e500v1 or e500v2.
|
2008-06-16 14:41:32 +00:00
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
config PPC_FPU
|
|
|
|
|
bool
|
|
|
|
|
default y if PPC64
|
|
|
|
|
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 12:42:18 +00:00
|
|
|
config PPC_8xx_PERF_EVENT
|
|
|
|
|
bool "PPC 8xx perf events"
|
|
|
|
|
depends on PPC_8xx && PERF_EVENTS
|
|
|
|
|
help
|
|
|
|
|
This is Performance Events support for PPC 8xx. The 8xx doesn't
|
|
|
|
|
have a PMU but some events are emulated using 8xx features.
|
|
|
|
|
|
2009-10-16 23:31:48 +00:00
|
|
|
config FSL_EMB_PERFMON
|
|
|
|
|
bool "Freescale Embedded Perfmon"
|
|
|
|
|
depends on E500 || PPC_83xx
|
|
|
|
|
help
|
|
|
|
|
This is the Performance Monitor support found on the e500 core
|
|
|
|
|
and some e300 cores (c3 and c4). Select this only if your
|
|
|
|
|
core supports the Embedded Performance Monitor APU
|
|
|
|
|
|
2010-02-26 00:09:45 +00:00
|
|
|
config FSL_EMB_PERF_EVENT
|
|
|
|
|
bool
|
|
|
|
|
depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS
|
|
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
config FSL_EMB_PERF_EVENT_E500
|
|
|
|
|
bool
|
|
|
|
|
depends on FSL_EMB_PERF_EVENT && E500
|
|
|
|
|
default y
|
|
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
config 4xx
|
|
|
|
|
bool
|
|
|
|
|
depends on 40x || 44x
|
|
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
config BOOKE
|
|
|
|
|
bool
|
2009-07-23 23:15:59 +00:00
|
|
|
depends on E200 || E500 || 44x || PPC_BOOK3E
|
2007-06-12 16:30:17 +00:00
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
config FSL_BOOKE
|
|
|
|
|
bool
|
2010-10-08 13:32:11 +00:00
|
|
|
depends on (E200 || E500) && PPC32
|
2007-06-12 16:30:17 +00:00
|
|
|
default y
|
|
|
|
|
|
2010-10-08 13:32:11 +00:00
|
|
|
# this is for common code between PPC32 & PPC64 FSL BOOKE
|
|
|
|
|
config PPC_FSL_BOOK3E
|
|
|
|
|
bool
|
|
|
|
|
select FSL_EMB_PERFMON
|
2011-05-10 19:29:42 +00:00
|
|
|
select PPC_SMP_MUXED_IPI
|
2011-10-10 10:50:44 +00:00
|
|
|
select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
|
2012-11-14 18:49:49 +00:00
|
|
|
select PPC_DOORBELL
|
2010-10-08 13:32:11 +00:00
|
|
|
default y if FSL_BOOKE
|
2008-02-05 00:27:55 +00:00
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
config PTE_64BIT
|
|
|
|
|
bool
|
2008-09-24 16:01:24 +00:00
|
|
|
depends on 44x || E500 || PPC_86xx
|
|
|
|
|
default y if PHYS_64BIT
|
2007-06-12 16:30:17 +00:00
|
|
|
|
|
|
|
|
config PHYS_64BIT
|
2008-09-24 16:01:24 +00:00
|
|
|
bool 'Large physical address support' if E500 || PPC_86xx
|
|
|
|
|
depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
|
2007-06-12 16:30:17 +00:00
|
|
|
---help---
|
|
|
|
|
This option enables kernel support for larger than 32-bit physical
|
2008-09-24 16:01:24 +00:00
|
|
|
addresses. This feature may not be available on all cores.
|
|
|
|
|
|
|
|
|
|
If you have more than 3.5GB of RAM or so, you also need to enable
|
|
|
|
|
SWIOTLB under Kernel Options for this to work. The actual number
|
|
|
|
|
is platform-dependent.
|
2007-06-12 16:30:17 +00:00
|
|
|
|
|
|
|
|
If in doubt, say N here.
|
|
|
|
|
|
|
|
|
|
config ALTIVEC
|
|
|
|
|
bool "AltiVec Support"
|
2014-07-10 02:29:25 +00:00
|
|
|
depends on 6xx || PPC_BOOK3S_64 || (PPC_E500MC && PPC64)
|
2007-06-12 16:30:17 +00:00
|
|
|
---help---
|
|
|
|
|
This option enables kernel support for the Altivec extensions to the
|
|
|
|
|
PowerPC processor. The kernel currently supports saving and restoring
|
|
|
|
|
altivec registers, and turning on the 'altivec enable' bit so user
|
|
|
|
|
processes can execute altivec instructions.
|
|
|
|
|
|
|
|
|
|
This option is only usefully if you have a processor that supports
|
|
|
|
|
altivec (G4, otherwise known as 74xx series), but does not have
|
|
|
|
|
any affect on a non-altivec cpu (it does, however add code to the
|
|
|
|
|
kernel).
|
|
|
|
|
|
|
|
|
|
If in doubt, say Y here.
|
|
|
|
|
|
2008-06-25 04:07:18 +00:00
|
|
|
config VSX
|
|
|
|
|
bool "VSX Support"
|
2014-07-10 02:29:25 +00:00
|
|
|
depends on PPC_BOOK3S_64 && ALTIVEC && PPC_FPU
|
2008-06-25 04:07:18 +00:00
|
|
|
---help---
|
|
|
|
|
|
|
|
|
|
This option enables kernel support for the Vector Scaler extensions
|
|
|
|
|
to the PowerPC processor. The kernel currently supports saving and
|
|
|
|
|
restoring VSX registers, and turning on the 'VSX enable' bit so user
|
|
|
|
|
processes can execute VSX instructions.
|
|
|
|
|
|
|
|
|
|
This option is only useful if you have a processor that supports
|
|
|
|
|
VSX (P7 and above), but does not have any affect on a non-VSX
|
|
|
|
|
CPUs (it does, however add code to the kernel).
|
|
|
|
|
|
|
|
|
|
If in doubt, say Y here.
|
|
|
|
|
|
2014-08-20 13:09:03 +00:00
|
|
|
config SPE_POSSIBLE
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on E200 || (E500 && !PPC_E500MC)
|
|
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
config SPE
|
|
|
|
|
bool "SPE Support"
|
2014-08-20 13:09:03 +00:00
|
|
|
depends on SPE_POSSIBLE
|
2007-06-12 16:30:17 +00:00
|
|
|
default y
|
|
|
|
|
---help---
|
|
|
|
|
This option enables kernel support for the Signal Processing
|
|
|
|
|
Extensions (SPE) to the PowerPC processor. The kernel currently
|
|
|
|
|
supports saving and restoring SPE registers, and turning on the
|
|
|
|
|
'spe enable' bit so user processes can execute SPE instructions.
|
|
|
|
|
|
|
|
|
|
This option is only useful if you have a processor that supports
|
|
|
|
|
SPE (e500, otherwise known as 85xx series), but does not have any
|
|
|
|
|
effect on a non-spe cpu (it does, however add code to the kernel).
|
|
|
|
|
|
|
|
|
|
If in doubt, say Y here.
|
|
|
|
|
|
|
|
|
|
config PPC_STD_MMU
|
2009-06-02 21:17:37 +00:00
|
|
|
def_bool y
|
|
|
|
|
depends on PPC_BOOK3S
|
2007-06-12 16:30:17 +00:00
|
|
|
|
|
|
|
|
config PPC_STD_MMU_32
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on PPC_STD_MMU && PPC32
|
|
|
|
|
|
2008-12-18 19:13:24 +00:00
|
|
|
config PPC_STD_MMU_64
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on PPC_STD_MMU && PPC64
|
|
|
|
|
|
2016-04-29 13:25:53 +00:00
|
|
|
config PPC_RADIX_MMU
|
|
|
|
|
bool "Radix MMU Support"
|
|
|
|
|
depends on PPC_BOOK3S_64
|
2017-07-06 22:39:20 +00:00
|
|
|
select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
|
2016-04-29 13:25:53 +00:00
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Power ISA 3.0 Radix style MMU. Currently this
|
|
|
|
|
is only implemented by IBM Power9 CPUs, if you don't have one of them
|
|
|
|
|
you can probably disable this.
|
|
|
|
|
|
2017-07-06 22:39:05 +00:00
|
|
|
config ARCH_ENABLE_HUGEPAGE_MIGRATION
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on PPC_BOOK3S_64 && HUGETLB_PAGE && MIGRATION
|
|
|
|
|
|
|
|
|
|
|
2008-12-18 19:13:24 +00:00
|
|
|
config PPC_MMU_NOHASH
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on !PPC_STD_MMU
|
|
|
|
|
|
2009-02-12 22:12:40 +00:00
|
|
|
config PPC_BOOK3E_MMU
|
|
|
|
|
def_bool y
|
2009-07-23 23:15:59 +00:00
|
|
|
depends on FSL_BOOKE || PPC_BOOK3E
|
2009-02-12 22:12:40 +00:00
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
config PPC_MM_SLICES
|
|
|
|
|
bool
|
2017-03-21 17:29:51 +00:00
|
|
|
default y if PPC_STD_MMU_64
|
2007-06-12 16:30:17 +00:00
|
|
|
default n
|
|
|
|
|
|
2009-06-17 11:50:04 +00:00
|
|
|
config PPC_HAVE_PMU_SUPPORT
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config PPC_PERF_CTRS
|
|
|
|
|
def_bool y
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT
|
2009-06-17 11:50:04 +00:00
|
|
|
help
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
This enables the powerpc-specific perf_event back-end.
|
2009-06-17 11:50:04 +00:00
|
|
|
|
2017-04-05 02:44:49 +00:00
|
|
|
config FORCE_SMP
|
|
|
|
|
# Allow platforms to force SMP=y by selecting this
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
select SMP
|
|
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
config SMP
|
2010-03-05 10:43:12 +00:00
|
|
|
depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x
|
2017-04-05 07:54:49 +00:00
|
|
|
select GENERIC_IRQ_MIGRATION
|
2017-04-05 02:44:49 +00:00
|
|
|
bool "Symmetric multi-processing support" if !FORCE_SMP
|
2007-06-12 16:30:17 +00:00
|
|
|
---help---
|
|
|
|
|
This enables support for systems with more than one CPU. If you have
|
|
|
|
|
a system with only one CPU, say N. If you have a system with more
|
|
|
|
|
than one CPU, say Y. Note that the kernel does not currently
|
|
|
|
|
support SMP machines with 603/603e/603ev or PPC750 ("G3") processors
|
|
|
|
|
since they have inadequate hardware support for multiprocessor
|
|
|
|
|
operation.
|
|
|
|
|
|
|
|
|
|
If you say N here, the kernel will run on single and multiprocessor
|
|
|
|
|
machines, but will use only one CPU of a multiprocessor machine. If
|
|
|
|
|
you say Y here, the kernel will run on single-processor machines.
|
|
|
|
|
On a single-processor machine, the kernel will run faster if you say
|
|
|
|
|
N here.
|
|
|
|
|
|
|
|
|
|
If you don't know what to do here, say N.
|
|
|
|
|
|
|
|
|
|
config NR_CPUS
|
2009-05-17 15:13:16 +00:00
|
|
|
int "Maximum number of CPUs (2-8192)"
|
|
|
|
|
range 2 8192
|
2007-06-12 16:30:17 +00:00
|
|
|
depends on SMP
|
|
|
|
|
default "32" if PPC64
|
|
|
|
|
default "4"
|
|
|
|
|
|
|
|
|
|
config NOT_COHERENT_CACHE
|
|
|
|
|
bool
|
2017-08-08 11:58:54 +00:00
|
|
|
depends on 4xx || PPC_8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON
|
2010-03-05 10:43:12 +00:00
|
|
|
default n if PPC_47x
|
2007-06-12 16:30:17 +00:00
|
|
|
default y
|
|
|
|
|
|
2007-07-17 22:21:29 +00:00
|
|
|
config CHECK_CACHE_COHERENCY
|
2007-06-12 16:30:17 +00:00
|
|
|
bool
|
|
|
|
|
|
2012-11-14 18:49:49 +00:00
|
|
|
config PPC_DOORBELL
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2007-06-12 16:30:17 +00:00
|
|
|
endmenu
|
2013-11-20 11:15:05 +00:00
|
|
|
|
2015-05-11 10:01:02 +00:00
|
|
|
config VDSO32
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on PPC32 || CPU_BIG_ENDIAN
|
|
|
|
|
help
|
|
|
|
|
This symbol controls whether we build the 32-bit VDSO. We obviously
|
|
|
|
|
want to do that if we're building a 32-bit kernel. If we're building
|
|
|
|
|
a 64-bit kernel then we only want a 32-bit VDSO if we're building for
|
|
|
|
|
big endian. That is because the only little endian configuration we
|
|
|
|
|
support is ppc64le which is 64-bit only.
|
|
|
|
|
|
2013-11-21 05:33:55 +00:00
|
|
|
choice
|
|
|
|
|
prompt "Endianness selection"
|
|
|
|
|
default CPU_BIG_ENDIAN
|
2013-11-20 11:15:05 +00:00
|
|
|
help
|
|
|
|
|
This option selects whether a big endian or little endian kernel will
|
|
|
|
|
be built.
|
|
|
|
|
|
2013-11-21 05:33:55 +00:00
|
|
|
config CPU_BIG_ENDIAN
|
|
|
|
|
bool "Build big endian kernel"
|
|
|
|
|
help
|
|
|
|
|
Build a big endian kernel.
|
|
|
|
|
|
|
|
|
|
If unsure, select this option.
|
|
|
|
|
|
|
|
|
|
config CPU_LITTLE_ENDIAN
|
|
|
|
|
bool "Build little endian kernel"
|
2015-04-22 05:36:50 +00:00
|
|
|
depends on PPC_BOOK3S_64
|
2014-04-24 07:23:39 +00:00
|
|
|
select PPC64_BOOT_WRAPPER
|
2013-11-21 05:33:55 +00:00
|
|
|
help
|
|
|
|
|
Build a little endian kernel.
|
|
|
|
|
|
2013-11-20 11:15:05 +00:00
|
|
|
Note that if cross compiling a little endian kernel,
|
|
|
|
|
CROSS_COMPILE must point to a toolchain capable of targeting
|
|
|
|
|
little endian powerpc.
|
2013-11-21 05:33:55 +00:00
|
|
|
|
|
|
|
|
endchoice
|
2014-04-24 07:23:39 +00:00
|
|
|
|
|
|
|
|
config PPC64_BOOT_WRAPPER
|
|
|
|
|
def_bool n
|
|
|
|
|
depends on CPU_LITTLE_ENDIAN
|