2019-05-27 06:55:05 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2005-04-16 22:20:36 +00:00
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/*
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* Driver for Digigram miXart soundcards
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*
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* low level interface with interrupt handling and mail box implementation
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*
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* Copyright (c) 2003 by Digigram <alsa@digigram.com>
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*/
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#include <linux/interrupt.h>
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2006-01-16 15:34:20 +00:00
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#include <linux/mutex.h>
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2014-02-25 16:51:46 +00:00
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#include <linux/pci.h>
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2015-01-28 15:49:33 +00:00
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#include <linux/io.h>
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2006-01-16 15:34:20 +00:00
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2005-04-16 22:20:36 +00:00
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#include <sound/core.h>
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#include "mixart.h"
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#include "mixart_hwdep.h"
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#include "mixart_core.h"
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#define MSG_TIMEOUT_JIFFIES (400 * HZ) / 1000 /* 400 ms */
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#define MSG_DESCRIPTOR_SIZE 0x24
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#define MSG_HEADER_SIZE (MSG_DESCRIPTOR_SIZE + 4)
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#define MSG_DEFAULT_SIZE 512
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#define MSG_TYPE_MASK 0x00000003 /* mask for following types */
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#define MSG_TYPE_NOTIFY 0 /* embedded -> driver (only notification, do not get_msg() !) */
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#define MSG_TYPE_COMMAND 1 /* driver <-> embedded (a command has no answer) */
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#define MSG_TYPE_REQUEST 2 /* driver -> embedded (request will get an answer back) */
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#define MSG_TYPE_ANSWER 3 /* embedded -> driver */
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#define MSG_CANCEL_NOTIFY_MASK 0x80000000 /* this bit is set for a notification that has been canceled */
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2005-11-17 14:01:08 +00:00
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static int retrieve_msg_frame(struct mixart_mgr *mgr, u32 *msg_frame)
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2005-04-16 22:20:36 +00:00
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{
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/* read the message frame fifo */
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u32 headptr, tailptr;
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tailptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_POST_TAIL));
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headptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_POST_HEAD));
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if (tailptr == headptr)
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return 0; /* no message posted */
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2008-08-08 15:12:14 +00:00
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if (tailptr < MSG_OUTBOUND_POST_STACK)
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return 0; /* error */
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if (tailptr >= MSG_OUTBOUND_POST_STACK + MSG_BOUND_STACK_SIZE)
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return 0; /* error */
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2005-04-16 22:20:36 +00:00
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*msg_frame = readl_be(MIXART_MEM(mgr, tailptr));
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/* increment the tail index */
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tailptr += 4;
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if( tailptr >= (MSG_OUTBOUND_POST_STACK+MSG_BOUND_STACK_SIZE) )
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tailptr = MSG_OUTBOUND_POST_STACK;
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writel_be(tailptr, MIXART_MEM(mgr, MSG_OUTBOUND_POST_TAIL));
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return 1;
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}
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2005-11-17 14:01:08 +00:00
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static int get_msg(struct mixart_mgr *mgr, struct mixart_msg *resp,
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u32 msg_frame_address )
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2005-04-16 22:20:36 +00:00
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{
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u32 headptr;
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u32 size;
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int err;
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#ifndef __BIG_ENDIAN
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unsigned int i;
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#endif
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2014-09-10 09:48:07 +00:00
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mutex_lock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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err = 0;
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/* copy message descriptor from miXart to driver */
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size = readl_be(MIXART_MEM(mgr, msg_frame_address)); /* size of descriptor + response */
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resp->message_id = readl_be(MIXART_MEM(mgr, msg_frame_address + 4)); /* dwMessageID */
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resp->uid.object_id = readl_be(MIXART_MEM(mgr, msg_frame_address + 8)); /* uidDest */
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resp->uid.desc = readl_be(MIXART_MEM(mgr, msg_frame_address + 12)); /* */
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if( (size < MSG_DESCRIPTOR_SIZE) || (resp->size < (size - MSG_DESCRIPTOR_SIZE))) {
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err = -EINVAL;
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2014-02-25 16:51:46 +00:00
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dev_err(&mgr->pci->dev,
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"problem with response size = %d\n", size);
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2005-04-16 22:20:36 +00:00
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goto _clean_exit;
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}
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size -= MSG_DESCRIPTOR_SIZE;
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memcpy_fromio(resp->data, MIXART_MEM(mgr, msg_frame_address + MSG_HEADER_SIZE ), size);
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resp->size = size;
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/* swap if necessary */
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#ifndef __BIG_ENDIAN
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size /= 4; /* u32 size */
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for(i=0; i < size; i++) {
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2018-07-25 21:24:05 +00:00
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((u32*)resp->data)[i] = be32_to_cpu(((__be32*)resp->data)[i]);
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2005-04-16 22:20:36 +00:00
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}
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#endif
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/*
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* free message frame address
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*/
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headptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_FREE_HEAD));
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if( (headptr < MSG_OUTBOUND_FREE_STACK) || ( headptr >= (MSG_OUTBOUND_FREE_STACK+MSG_BOUND_STACK_SIZE))) {
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err = -EINVAL;
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goto _clean_exit;
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}
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/* give address back to outbound fifo */
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writel_be(msg_frame_address, MIXART_MEM(mgr, headptr));
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/* increment the outbound free head */
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headptr += 4;
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if( headptr >= (MSG_OUTBOUND_FREE_STACK+MSG_BOUND_STACK_SIZE) )
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headptr = MSG_OUTBOUND_FREE_STACK;
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writel_be(headptr, MIXART_MEM(mgr, MSG_OUTBOUND_FREE_HEAD));
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_clean_exit:
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2014-09-10 09:48:07 +00:00
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mutex_unlock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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return err;
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}
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/*
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* send a message to miXart. return: the msg_frame used for this message
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*/
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/* call with mgr->msg_lock held! */
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2005-11-17 14:01:08 +00:00
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static int send_msg( struct mixart_mgr *mgr,
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struct mixart_msg *msg,
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2005-04-16 22:20:36 +00:00
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int max_answersize,
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int mark_pending,
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u32 *msg_event)
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{
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u32 headptr, tailptr;
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u32 msg_frame_address;
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2014-07-01 11:32:58 +00:00
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int i;
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2005-04-16 22:20:36 +00:00
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2008-08-08 15:12:14 +00:00
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if (snd_BUG_ON(msg->size % 4))
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return -EINVAL;
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2005-04-16 22:20:36 +00:00
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/* get message frame address */
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tailptr = readl_be(MIXART_MEM(mgr, MSG_INBOUND_FREE_TAIL));
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headptr = readl_be(MIXART_MEM(mgr, MSG_INBOUND_FREE_HEAD));
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if (tailptr == headptr) {
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2014-02-25 16:51:46 +00:00
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dev_err(&mgr->pci->dev, "error: no message frame available\n");
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2005-04-16 22:20:36 +00:00
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return -EBUSY;
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}
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if( (tailptr < MSG_INBOUND_FREE_STACK) || (tailptr >= (MSG_INBOUND_FREE_STACK+MSG_BOUND_STACK_SIZE))) {
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return -EINVAL;
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}
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msg_frame_address = readl_be(MIXART_MEM(mgr, tailptr));
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writel(0, MIXART_MEM(mgr, tailptr)); /* set address to zero on this fifo position */
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/* increment the inbound free tail */
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tailptr += 4;
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if( tailptr >= (MSG_INBOUND_FREE_STACK+MSG_BOUND_STACK_SIZE) )
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tailptr = MSG_INBOUND_FREE_STACK;
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writel_be(tailptr, MIXART_MEM(mgr, MSG_INBOUND_FREE_TAIL));
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/* TODO : use memcpy_toio() with intermediate buffer to copy the message */
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/* copy message descriptor to card memory */
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writel_be( msg->size + MSG_DESCRIPTOR_SIZE, MIXART_MEM(mgr, msg_frame_address) ); /* size of descriptor + request */
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writel_be( msg->message_id , MIXART_MEM(mgr, msg_frame_address + 4) ); /* dwMessageID */
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writel_be( msg->uid.object_id, MIXART_MEM(mgr, msg_frame_address + 8) ); /* uidDest */
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writel_be( msg->uid.desc, MIXART_MEM(mgr, msg_frame_address + 12) ); /* */
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writel_be( MSG_DESCRIPTOR_SIZE, MIXART_MEM(mgr, msg_frame_address + 16) ); /* SizeHeader */
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writel_be( MSG_DESCRIPTOR_SIZE, MIXART_MEM(mgr, msg_frame_address + 20) ); /* OffsetDLL_T16 */
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writel_be( msg->size, MIXART_MEM(mgr, msg_frame_address + 24) ); /* SizeDLL_T16 */
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writel_be( MSG_DESCRIPTOR_SIZE, MIXART_MEM(mgr, msg_frame_address + 28) ); /* OffsetDLL_DRV */
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writel_be( 0, MIXART_MEM(mgr, msg_frame_address + 32) ); /* SizeDLL_DRV */
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writel_be( MSG_DESCRIPTOR_SIZE + max_answersize, MIXART_MEM(mgr, msg_frame_address + 36) ); /* dwExpectedAnswerSize */
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/* copy message data to card memory */
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for( i=0; i < msg->size; i+=4 ) {
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writel_be( *(u32*)(msg->data + i), MIXART_MEM(mgr, MSG_HEADER_SIZE + msg_frame_address + i) );
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}
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if( mark_pending ) {
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if( *msg_event ) {
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/* the pending event is the notification we wait for ! */
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mgr->pending_event = *msg_event;
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}
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else {
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/* the pending event is the answer we wait for (same address than the request)! */
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mgr->pending_event = msg_frame_address;
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/* copy address back to caller */
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*msg_event = msg_frame_address;
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}
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}
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/* mark the frame as a request (will have an answer) */
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msg_frame_address |= MSG_TYPE_REQUEST;
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/* post the frame */
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headptr = readl_be(MIXART_MEM(mgr, MSG_INBOUND_POST_HEAD));
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if( (headptr < MSG_INBOUND_POST_STACK) || (headptr >= (MSG_INBOUND_POST_STACK+MSG_BOUND_STACK_SIZE))) {
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return -EINVAL;
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}
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writel_be(msg_frame_address, MIXART_MEM(mgr, headptr));
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/* increment the inbound post head */
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headptr += 4;
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if( headptr >= (MSG_INBOUND_POST_STACK+MSG_BOUND_STACK_SIZE) )
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headptr = MSG_INBOUND_POST_STACK;
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writel_be(headptr, MIXART_MEM(mgr, MSG_INBOUND_POST_HEAD));
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return 0;
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}
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2005-11-17 14:01:08 +00:00
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int snd_mixart_send_msg(struct mixart_mgr *mgr, struct mixart_msg *request, int max_resp_size, void *resp_data)
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2005-04-16 22:20:36 +00:00
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{
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2005-11-17 14:01:08 +00:00
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struct mixart_msg resp;
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2005-04-16 22:20:36 +00:00
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u32 msg_frame = 0; /* set to 0, so it's no notification to wait for, but the answer */
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int err;
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2017-06-20 10:06:13 +00:00
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wait_queue_entry_t wait;
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2005-04-16 22:20:36 +00:00
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long timeout;
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init_waitqueue_entry(&wait, current);
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2014-09-10 09:48:07 +00:00
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mutex_lock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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/* send the message */
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err = send_msg(mgr, request, max_resp_size, 1, &msg_frame); /* send and mark the answer pending */
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if (err) {
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2014-09-10 09:48:07 +00:00
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mutex_unlock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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return err;
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}
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set_current_state(TASK_UNINTERRUPTIBLE);
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add_wait_queue(&mgr->msg_sleep, &wait);
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2014-09-10 09:48:07 +00:00
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mutex_unlock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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timeout = schedule_timeout(MSG_TIMEOUT_JIFFIES);
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remove_wait_queue(&mgr->msg_sleep, &wait);
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if (! timeout) {
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/* error - no ack */
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2014-02-25 16:51:46 +00:00
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dev_err(&mgr->pci->dev,
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"error: no response on msg %x\n", msg_frame);
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2005-04-16 22:20:36 +00:00
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return -EIO;
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}
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2005-11-17 14:01:08 +00:00
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/* retrieve the answer into the same struct mixart_msg */
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2005-04-16 22:20:36 +00:00
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resp.message_id = 0;
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2005-11-17 14:01:08 +00:00
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resp.uid = (struct mixart_uid){0,0};
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2005-04-16 22:20:36 +00:00
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resp.data = resp_data;
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resp.size = max_resp_size;
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err = get_msg(mgr, &resp, msg_frame);
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if( request->message_id != resp.message_id )
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2014-02-25 16:51:46 +00:00
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dev_err(&mgr->pci->dev, "RESPONSE ERROR!\n");
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2005-04-16 22:20:36 +00:00
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return err;
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}
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2005-11-17 14:01:08 +00:00
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int snd_mixart_send_msg_wait_notif(struct mixart_mgr *mgr,
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struct mixart_msg *request, u32 notif_event)
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2005-04-16 22:20:36 +00:00
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{
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int err;
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2017-06-20 10:06:13 +00:00
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wait_queue_entry_t wait;
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2005-04-16 22:20:36 +00:00
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long timeout;
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2008-08-08 15:12:14 +00:00
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if (snd_BUG_ON(!notif_event))
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return -EINVAL;
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if (snd_BUG_ON((notif_event & MSG_TYPE_MASK) != MSG_TYPE_NOTIFY))
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return -EINVAL;
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if (snd_BUG_ON(notif_event & MSG_CANCEL_NOTIFY_MASK))
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return -EINVAL;
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2005-04-16 22:20:36 +00:00
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init_waitqueue_entry(&wait, current);
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2014-09-10 09:48:07 +00:00
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mutex_lock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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/* send the message */
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err = send_msg(mgr, request, MSG_DEFAULT_SIZE, 1, ¬if_event); /* send and mark the notification event pending */
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if(err) {
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2014-09-10 09:48:07 +00:00
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mutex_unlock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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return err;
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}
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set_current_state(TASK_UNINTERRUPTIBLE);
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add_wait_queue(&mgr->msg_sleep, &wait);
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2014-09-10 09:48:07 +00:00
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mutex_unlock(&mgr->msg_lock);
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2005-04-16 22:20:36 +00:00
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timeout = schedule_timeout(MSG_TIMEOUT_JIFFIES);
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remove_wait_queue(&mgr->msg_sleep, &wait);
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if (! timeout) {
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/* error - no ack */
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2014-02-25 16:51:46 +00:00
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|
|
dev_err(&mgr->pci->dev,
|
|
|
|
"error: notification %x not received\n", notif_event);
|
2005-04-16 22:20:36 +00:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-11-17 14:01:08 +00:00
|
|
|
int snd_mixart_send_msg_nonblock(struct mixart_mgr *mgr, struct mixart_msg *request)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
u32 message_frame;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/* just send the message (do not mark it as a pending one) */
|
2014-09-10 09:48:07 +00:00
|
|
|
mutex_lock(&mgr->msg_lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
err = send_msg(mgr, request, MSG_DEFAULT_SIZE, 0, &message_frame);
|
2014-09-10 09:48:07 +00:00
|
|
|
mutex_unlock(&mgr->msg_lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-11-17 14:01:08 +00:00
|
|
|
/* the answer will be handled by snd_struct mixart_msgasklet() */
|
2005-04-16 22:20:36 +00:00
|
|
|
atomic_inc(&mgr->msg_processed);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2014-09-10 09:48:07 +00:00
|
|
|
/* common buffer of interrupt to send/receive messages */
|
2005-04-16 22:20:36 +00:00
|
|
|
static u32 mixart_msg_data[MSG_DEFAULT_SIZE / 4];
|
|
|
|
|
|
|
|
|
2014-09-10 09:48:07 +00:00
|
|
|
static void snd_mixart_process_msg(struct mixart_mgr *mgr)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2005-11-17 14:01:08 +00:00
|
|
|
struct mixart_msg resp;
|
2005-04-16 22:20:36 +00:00
|
|
|
u32 msg, addr, type;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
while (mgr->msg_fifo_readptr != mgr->msg_fifo_writeptr) {
|
|
|
|
msg = mgr->msg_fifo[mgr->msg_fifo_readptr];
|
|
|
|
mgr->msg_fifo_readptr++;
|
|
|
|
mgr->msg_fifo_readptr %= MSG_FIFO_SIZE;
|
|
|
|
|
|
|
|
/* process the message ... */
|
|
|
|
addr = msg & ~MSG_TYPE_MASK;
|
|
|
|
type = msg & MSG_TYPE_MASK;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case MSG_TYPE_ANSWER:
|
|
|
|
/* answer to a message on that we did not wait for (send_msg_nonblock) */
|
|
|
|
resp.message_id = 0;
|
|
|
|
resp.data = mixart_msg_data;
|
|
|
|
resp.size = sizeof(mixart_msg_data);
|
|
|
|
err = get_msg(mgr, &resp, addr);
|
|
|
|
if( err < 0 ) {
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_err(&mgr->pci->dev,
|
2014-09-10 09:48:07 +00:00
|
|
|
"error(%d) reading mf %x\n",
|
2014-02-25 16:51:46 +00:00
|
|
|
err, msg);
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch(resp.message_id) {
|
|
|
|
case MSG_STREAM_START_INPUT_STAGE_PACKET:
|
|
|
|
case MSG_STREAM_START_OUTPUT_STAGE_PACKET:
|
|
|
|
case MSG_STREAM_STOP_INPUT_STAGE_PACKET:
|
|
|
|
case MSG_STREAM_STOP_OUTPUT_STAGE_PACKET:
|
|
|
|
if(mixart_msg_data[0])
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_err(&mgr->pci->dev,
|
2014-09-10 09:48:07 +00:00
|
|
|
"error MSG_STREAM_ST***_***PUT_STAGE_PACKET status=%x\n",
|
2014-02-25 16:51:46 +00:00
|
|
|
mixart_msg_data[0]);
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
|
|
|
default:
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_dbg(&mgr->pci->dev,
|
2014-09-10 09:48:07 +00:00
|
|
|
"received mf(%x) : msg_id(%x) uid(%x, %x) size(%zd)\n",
|
2005-04-16 22:20:36 +00:00
|
|
|
msg, resp.message_id, resp.uid.object_id, resp.uid.desc, resp.size);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MSG_TYPE_NOTIFY:
|
|
|
|
/* msg contains no address ! do not get_msg() ! */
|
|
|
|
case MSG_TYPE_COMMAND:
|
|
|
|
/* get_msg() necessary */
|
|
|
|
default:
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_err(&mgr->pci->dev,
|
2014-09-10 09:48:07 +00:00
|
|
|
"doesn't know what to do with message %x\n",
|
2014-02-25 16:51:46 +00:00
|
|
|
msg);
|
2005-04-16 22:20:36 +00:00
|
|
|
} /* switch type */
|
|
|
|
|
|
|
|
/* decrement counter */
|
|
|
|
atomic_dec(&mgr->msg_processed);
|
|
|
|
|
|
|
|
} /* while there is a msg in fifo */
|
|
|
|
}
|
|
|
|
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 13:55:46 +00:00
|
|
|
irqreturn_t snd_mixart_interrupt(int irq, void *dev_id)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2005-11-17 14:01:08 +00:00
|
|
|
struct mixart_mgr *mgr = dev_id;
|
2005-04-16 22:20:36 +00:00
|
|
|
u32 it_reg;
|
|
|
|
|
|
|
|
it_reg = readl_le(MIXART_REG(mgr, MIXART_PCI_OMISR_OFFSET));
|
|
|
|
if( !(it_reg & MIXART_OIDI) ) {
|
|
|
|
/* this device did not cause the interrupt */
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* mask all interrupts */
|
|
|
|
writel_le(MIXART_HOST_ALL_INTERRUPT_MASKED, MIXART_REG(mgr, MIXART_PCI_OMIMR_OFFSET));
|
|
|
|
|
|
|
|
/* outdoorbell register clear */
|
|
|
|
it_reg = readl(MIXART_REG(mgr, MIXART_PCI_ODBR_OFFSET));
|
|
|
|
writel(it_reg, MIXART_REG(mgr, MIXART_PCI_ODBR_OFFSET));
|
|
|
|
|
|
|
|
/* clear interrupt */
|
|
|
|
writel_le( MIXART_OIDI, MIXART_REG(mgr, MIXART_PCI_OMISR_OFFSET) );
|
|
|
|
|
2014-09-10 09:48:07 +00:00
|
|
|
return IRQ_WAKE_THREAD;
|
|
|
|
}
|
|
|
|
|
|
|
|
irqreturn_t snd_mixart_threaded_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct mixart_mgr *mgr = dev_id;
|
|
|
|
int err;
|
|
|
|
struct mixart_msg resp;
|
|
|
|
u32 msg;
|
|
|
|
|
|
|
|
mutex_lock(&mgr->lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
/* process interrupt */
|
|
|
|
while (retrieve_msg_frame(mgr, &msg)) {
|
|
|
|
|
|
|
|
switch (msg & MSG_TYPE_MASK) {
|
|
|
|
case MSG_TYPE_COMMAND:
|
|
|
|
resp.message_id = 0;
|
|
|
|
resp.data = mixart_msg_data;
|
|
|
|
resp.size = sizeof(mixart_msg_data);
|
|
|
|
err = get_msg(mgr, &resp, msg & ~MSG_TYPE_MASK);
|
|
|
|
if( err < 0 ) {
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_err(&mgr->pci->dev,
|
|
|
|
"interrupt: error(%d) reading mf %x\n",
|
|
|
|
err, msg);
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(resp.message_id == MSG_SERVICES_TIMER_NOTIFY) {
|
|
|
|
int i;
|
2005-11-17 14:01:08 +00:00
|
|
|
struct mixart_timer_notify *notify;
|
|
|
|
notify = (struct mixart_timer_notify *)mixart_msg_data;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
for(i=0; i<notify->stream_count; i++) {
|
|
|
|
|
|
|
|
u32 buffer_id = notify->streams[i].buffer_id;
|
|
|
|
unsigned int chip_number = (buffer_id & MIXART_NOTIFY_CARD_MASK) >> MIXART_NOTIFY_CARD_OFFSET; /* card0 to 3 */
|
|
|
|
unsigned int pcm_number = (buffer_id & MIXART_NOTIFY_PCM_MASK ) >> MIXART_NOTIFY_PCM_OFFSET; /* pcm0 to 3 */
|
|
|
|
unsigned int sub_number = buffer_id & MIXART_NOTIFY_SUBS_MASK; /* 0 to MIXART_PLAYBACK_STREAMS */
|
|
|
|
unsigned int is_capture = ((buffer_id & MIXART_NOTIFY_CAPT_MASK) != 0); /* playback == 0 / capture == 1 */
|
|
|
|
|
2005-11-17 14:01:08 +00:00
|
|
|
struct snd_mixart *chip = mgr->chip[chip_number];
|
|
|
|
struct mixart_stream *stream;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
if ((chip_number >= mgr->num_cards) || (pcm_number >= MIXART_PCM_TOTAL) || (sub_number >= MIXART_PLAYBACK_STREAMS)) {
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_err(&mgr->pci->dev,
|
|
|
|
"error MSG_SERVICES_TIMER_NOTIFY buffer_id (%x) pos(%d)\n",
|
2005-04-16 22:20:36 +00:00
|
|
|
buffer_id, notify->streams[i].sample_pos_low_part);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_capture)
|
|
|
|
stream = &chip->capture_stream[pcm_number];
|
|
|
|
else
|
|
|
|
stream = &chip->playback_stream[pcm_number][sub_number];
|
|
|
|
|
|
|
|
if (stream->substream && (stream->status == MIXART_STREAM_STATUS_RUNNING)) {
|
2005-11-17 14:01:08 +00:00
|
|
|
struct snd_pcm_runtime *runtime = stream->substream->runtime;
|
2005-04-16 22:20:36 +00:00
|
|
|
int elapsed = 0;
|
|
|
|
u64 sample_count = ((u64)notify->streams[i].sample_pos_high_part) << 32;
|
|
|
|
sample_count |= notify->streams[i].sample_pos_low_part;
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
u64 new_elapse_pos = stream->abs_period_elapsed + runtime->period_size;
|
|
|
|
|
|
|
|
if (new_elapse_pos > sample_count) {
|
|
|
|
break; /* while */
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
elapsed = 1;
|
|
|
|
stream->buf_periods++;
|
|
|
|
if (stream->buf_periods >= runtime->periods)
|
|
|
|
stream->buf_periods = 0;
|
|
|
|
|
|
|
|
stream->abs_period_elapsed = new_elapse_pos;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
stream->buf_period_frag = (u32)( sample_count - stream->abs_period_elapsed );
|
|
|
|
|
|
|
|
if(elapsed) {
|
2014-09-10 09:48:07 +00:00
|
|
|
mutex_unlock(&mgr->lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
snd_pcm_period_elapsed(stream->substream);
|
2014-09-10 09:48:07 +00:00
|
|
|
mutex_lock(&mgr->lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if(resp.message_id == MSG_SERVICES_REPORT_TRACES) {
|
|
|
|
if(resp.size > 1) {
|
|
|
|
#ifndef __BIG_ENDIAN
|
|
|
|
/* Traces are text: the swapped msg_data has to be swapped back ! */
|
|
|
|
int i;
|
|
|
|
for(i=0; i<(resp.size/4); i++) {
|
2018-07-25 21:24:05 +00:00
|
|
|
((__be32*)mixart_msg_data)[i] = cpu_to_be32((mixart_msg_data)[i]);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
((char*)mixart_msg_data)[resp.size - 1] = 0;
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_dbg(&mgr->pci->dev,
|
|
|
|
"MIXART TRACE : %s\n",
|
|
|
|
(char *)mixart_msg_data);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_dbg(&mgr->pci->dev, "command %x not handled\n",
|
|
|
|
resp.message_id);
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MSG_TYPE_NOTIFY:
|
|
|
|
if(msg & MSG_CANCEL_NOTIFY_MASK) {
|
|
|
|
msg &= ~MSG_CANCEL_NOTIFY_MASK;
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_err(&mgr->pci->dev,
|
|
|
|
"canceled notification %x !\n", msg);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2018-08-08 22:11:48 +00:00
|
|
|
/* fall through */
|
2005-04-16 22:20:36 +00:00
|
|
|
case MSG_TYPE_ANSWER:
|
|
|
|
/* answer or notification to a message we are waiting for*/
|
2014-09-10 09:48:07 +00:00
|
|
|
mutex_lock(&mgr->msg_lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
if( (msg & ~MSG_TYPE_MASK) == mgr->pending_event ) {
|
|
|
|
wake_up(&mgr->msg_sleep);
|
|
|
|
mgr->pending_event = 0;
|
|
|
|
}
|
|
|
|
/* answer to a message we did't want to wait for */
|
|
|
|
else {
|
|
|
|
mgr->msg_fifo[mgr->msg_fifo_writeptr] = msg;
|
|
|
|
mgr->msg_fifo_writeptr++;
|
|
|
|
mgr->msg_fifo_writeptr %= MSG_FIFO_SIZE;
|
2014-09-10 09:48:07 +00:00
|
|
|
snd_mixart_process_msg(mgr);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2014-09-10 09:48:07 +00:00
|
|
|
mutex_unlock(&mgr->msg_lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
|
|
|
case MSG_TYPE_REQUEST:
|
|
|
|
default:
|
2014-02-25 16:51:46 +00:00
|
|
|
dev_dbg(&mgr->pci->dev,
|
|
|
|
"interrupt received request %x\n", msg);
|
2005-04-16 22:20:36 +00:00
|
|
|
/* TODO : are there things to do here ? */
|
|
|
|
break;
|
|
|
|
} /* switch on msg type */
|
|
|
|
} /* while there are msgs */
|
|
|
|
|
|
|
|
/* allow interrupt again */
|
|
|
|
writel_le( MIXART_ALLOW_OUTBOUND_DOORBELL, MIXART_REG( mgr, MIXART_PCI_OMIMR_OFFSET));
|
|
|
|
|
2014-09-10 09:48:07 +00:00
|
|
|
mutex_unlock(&mgr->lock);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-11-17 14:01:08 +00:00
|
|
|
void snd_mixart_init_mailbox(struct mixart_mgr *mgr)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
writel( 0, MIXART_MEM( mgr, MSG_HOST_RSC_PROTECTION ) );
|
|
|
|
writel( 0, MIXART_MEM( mgr, MSG_AGENT_RSC_PROTECTION ) );
|
|
|
|
|
|
|
|
/* allow outbound messagebox to generate interrupts */
|
|
|
|
if(mgr->irq >= 0) {
|
|
|
|
writel_le( MIXART_ALLOW_OUTBOUND_DOORBELL, MIXART_REG( mgr, MIXART_PCI_OMIMR_OFFSET));
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2005-11-17 14:01:08 +00:00
|
|
|
void snd_mixart_exit_mailbox(struct mixart_mgr *mgr)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
/* no more interrupts on outbound messagebox */
|
|
|
|
writel_le( MIXART_HOST_ALL_INTERRUPT_MASKED, MIXART_REG( mgr, MIXART_PCI_OMIMR_OFFSET));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2005-11-17 14:01:08 +00:00
|
|
|
void snd_mixart_reset_board(struct mixart_mgr *mgr)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
/* reset miXart */
|
|
|
|
writel_be( 1, MIXART_REG(mgr, MIXART_BA1_BRUTAL_RESET_OFFSET) );
|
|
|
|
return;
|
|
|
|
}
|