linux/arch/arm/mach-omap2/prm2xxx_3xxx.c

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/*
* OMAP2/3 PRM module functions
*
* Copyright (C) 2010-2011 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
* Benoît Cousson
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <plat/prcm.h>
ARM: OMAP: Split plat/hardware.h, use local soc.h for omap2+ As the plat and mach includes need to disappear for single zImage work, we need to remove plat/hardware.h. Do this by splitting plat/hardware.h into omap1 and omap2+ specific files. The old plat/hardware.h already has omap1 only defines, so it gets moved to mach/hardware.h for omap1. For omap2+, we use the local soc.h that for now just includes the related SoC headers to keep this patch more readable. Note that the local soc.h still includes plat/cpu.h that can be dealt with in later patches. Let's also include plat/serial.h from common.h for all the board-*.c files. This allows making the include files local later on without patching these files again. Note that only minimal changes are done in this patch for the drivers/watchdog/omap_wdt.c driver to keep things compiling. Further patches are needed to eventually remove cpu_is_omap usage in the drivers. Also only minimal changes are done to sound/soc/omap/* to remove the unneeded includes and to define OMAP44XX_MCPDM_L3_BASE locally so there's no need to include omap44xx.h. While at it, also sort some of the includes in the standard way. Cc: linux-watchdog@vger.kernel.org Cc: alsa-devel@alsa-project.org Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jarkko Nikula <jarkko.nikula@bitmer.com> Cc: Liam Girdwood <lrg@ti.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-08-31 17:59:07 +00:00
#include "soc.h"
#include "common.h"
#include "vp.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"
static const struct omap_prcm_irq omap3_prcm_irqs[] = {
OMAP_PRCM_IRQ("wkup", 0, 0),
OMAP_PRCM_IRQ("io", 9, 1),
};
static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
.ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
.mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
.nr_regs = 1,
.irqs = omap3_prcm_irqs,
.nr_irqs = ARRAY_SIZE(omap3_prcm_irqs),
.irq = 11 + OMAP_INTC_START,
.read_pending_irqs = &omap3xxx_prm_read_pending_irqs,
.ocp_barrier = &omap3xxx_prm_ocp_barrier,
.save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
.restore_irqen = &omap3xxx_prm_restore_irqen,
};
u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{
return __raw_readl(prm_base + module + idx);
}
void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__raw_writel(val, prm_base + module + idx);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{
u32 v;
v = omap2_prm_read_mod_reg(module, idx);
v &= ~mask;
v |= bits;
omap2_prm_write_mod_reg(v, module, idx);
return v;
}
/* Read a PRM register, AND it, and shift the result down to bit 0 */
u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
{
u32 v;
v = omap2_prm_read_mod_reg(domain, idx);
v &= mask;
v >>= __ffs(mask);
return v;
}
u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
}
u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}
/**
* omap2_prm_is_hardreset_asserted - read the HW reset line state of
* submodules contained in the hwmod module
* @prm_mod: PRM submodule base (e.g. CORE_MOD)
* @shift: register bit shift corresponding to the reset line to check
*
* Returns 1 if the (sub)module hardreset line is currently asserted,
* 0 if the (sub)module hardreset line is not currently asserted, or
* -EINVAL if called while running on a non-OMAP2/3 chip.
*/
int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
{
if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
return -EINVAL;
return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
(1 << shift));
}
/**
* omap2_prm_assert_hardreset - assert the HW reset line of a submodule
* @prm_mod: PRM submodule base (e.g. CORE_MOD)
* @shift: register bit shift corresponding to the reset line to assert
*
* Some IPs like dsp or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* place the submodule into reset. Returns 0 upon success or -EINVAL
* upon an argument error.
*/
int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
{
u32 mask;
if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
return -EINVAL;
mask = 1 << shift;
omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
return 0;
}
/**
* omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
* @prm_mod: PRM submodule base (e.g. CORE_MOD)
* @rst_shift: register bit shift corresponding to the reset line to deassert
* @st_shift: register bit shift for the status of the deasserted submodule
*
* Some IPs like dsp or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* take the submodule out of reset and wait until the PRCM indicates
* that the reset has completed before returning. Returns 0 upon success or
* -EINVAL upon an argument error, -EEXIST if the submodule was already out
* of reset, or -EBUSY if the submodule did not exit reset promptly.
*/
int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
{
u32 rst, st;
int c;
if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
return -EINVAL;
rst = 1 << rst_shift;
st = 1 << st_shift;
/* Check the current status to avoid de-asserting the line twice */
if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
return -EEXIST;
/* Clear the reset status by writing 1 to the status bit */
omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
/* de-assert the reset control line */
omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
/* wait the status to be set */
omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
st),
MAX_MODULE_HARDRESET_WAIT, c);
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}
/* PRM VP */
/*
* struct omap3_vp - OMAP3 VP register access description.
* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
*/
struct omap3_vp {
u32 tranxdone_status;
};
static struct omap3_vp omap3_vp[] = {
[OMAP3_VP_VDD_MPU_ID] = {
.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
},
[OMAP3_VP_VDD_CORE_ID] = {
.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
},
};
#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
u32 omap3_prm_vp_check_txdone(u8 vp_id)
{
struct omap3_vp *vp = &omap3_vp[vp_id];
u32 irqstatus;
irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
return irqstatus & vp->tranxdone_status;
}
void omap3_prm_vp_clear_txdone(u8 vp_id)
{
struct omap3_vp *vp = &omap3_vp[vp_id];
omap2_prm_write_mod_reg(vp->tranxdone_status,
OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
}
u32 omap3_prm_vcvp_read(u8 offset)
{
return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
}
void omap3_prm_vcvp_write(u32 val, u8 offset)
{
omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
}
u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
{
return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
}
/**
* omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
* @events: ptr to a u32, preallocated by caller
*
* Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
* MPU IRQs, and store the result into the u32 pointed to by @events.
* No return value.
*/
void omap3xxx_prm_read_pending_irqs(unsigned long *events)
{
u32 mask, st;
/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
events[0] = mask & st;
}
/**
* omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
*
* Force any buffered writes to the PRM IP block to complete. Needed
* by the PRM IRQ handler, which reads and writes directly to the IP
* block, to avoid race conditions after acknowledging or clearing IRQ
* bits. No return value.
*/
void omap3xxx_prm_ocp_barrier(void)
{
omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
}
/**
* omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
* @saved_mask: ptr to a u32 array to save IRQENABLE bits
*
* Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
* must be allocated by the caller. Intended to be used in the PRM
* interrupt handler suspend callback. The OCP barrier is needed to
* ensure the write to disable PRM interrupts reaches the PRM before
* returning; otherwise, spurious interrupts might occur. No return
* value.
*/
void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
{
saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
OMAP3_PRM_IRQENABLE_MPU_OFFSET);
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
/* OCP barrier */
omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
}
/**
* omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
* @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
*
* Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
* to be used in the PRM interrupt handler resume callback to restore
* values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
* barrier should be needed here; any pending PRM interrupts will fire
* once the writes reach the PRM. No return value.
*/
void omap3xxx_prm_restore_irqen(u32 *saved_mask)
{
omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
OMAP3_PRM_IRQENABLE_MPU_OFFSET);
}
/**
* omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
*
* Clear any previously-latched I/O wakeup events and ensure that the
* I/O wakeup gates are aligned with the current mux settings. Works
* by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
* deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No
* return value.
*/
void omap3xxx_prm_reconfigure_io_chain(void)
{
int i = 0;
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
PM_WKEN);
omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
OMAP3430_ST_IO_CHAIN_MASK,
MAX_IOPAD_LATCH_TIME, i);
if (i == MAX_IOPAD_LATCH_TIME)
pr_warn("PRM: I/O chain clock line assertion timed out\n");
omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
PM_WKEN);
omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
PM_WKST);
omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
}
/**
* omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
*
* Activates the I/O wakeup event latches and allows events logged by
* those latches to signal a wakeup event to the PRCM. For I/O
* wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
* registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
* No return value.
*/
static void __init omap3xxx_prm_enable_io_wakeup(void)
{
if (omap3_has_io_wakeup())
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
PM_WKEN);
}
static int __init omap3xxx_prcm_init(void)
{
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge commit 99b59df0 (ARM: OMAP3: PM: fix shared PRCM interrupt leave disabled at boot) added IRQ_NOAUTOEN to the PRCM interrupt so it could be enabled later if needed. However, this commit was partially undone when merging the IO daisy chain rework in 9a17d88e (Merge tag 'omap-devel-c-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-pm This patch adds back the IRQ_NOAUTOEN fix that was removed by the merge resolution. This also fixes the following boot-time warning that showed up after merging the IO daisy chain rework: [ 3.849334] WARNING: at kernel/irq/manage.c:436 enable_irq+0x3c/0x78() [ 3.856231] Unbalanced enable for IRQ 297 [ 3.860473] Modules linked in: [ 3.863739] [<c001a114>] (unwind_backtrace+0x0/0xf0) from [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) [ 3.873687] [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) from [<c003c894>] (warn_slowpath_fmt+0x30/0x40) [ 3.883819] [<c003c894>] (warn_slowpath_fmt+0x30/0x40) from [<c00993e0>] (enable_irq+0x3c/0x78) [ 3.893035] [<c00993e0>] (enable_irq+0x3c/0x78) from [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) [ 3.902099] [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) from [<c067161c>] (init_machine_late+0x1c/0x28) [ 3.911773] [<c067161c>] (init_machine_late+0x1c/0x28) from [<c0008648>] (do_one_initcall+0x34/0x178) [ 3.921539] [<c0008648>] (do_one_initcall+0x34/0x178) from [<c066e8f4>] (kernel_init+0xfc/0x1c0) [ 3.930847] [<c066e8f4>] (kernel_init+0xfc/0x1c0) from [<c00140b0>] (kernel_thread_exit+0x0/0x8) [ 3.940246] ---[ end trace 55a0ad32ca2ca682 ]--- Reported-by: Javier Martinez Canillas <javier@dowhile0.org> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-29 14:03:34 +00:00
int ret = 0;
if (cpu_is_omap34xx()) {
omap3xxx_prm_enable_io_wakeup();
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge commit 99b59df0 (ARM: OMAP3: PM: fix shared PRCM interrupt leave disabled at boot) added IRQ_NOAUTOEN to the PRCM interrupt so it could be enabled later if needed. However, this commit was partially undone when merging the IO daisy chain rework in 9a17d88e (Merge tag 'omap-devel-c-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-pm This patch adds back the IRQ_NOAUTOEN fix that was removed by the merge resolution. This also fixes the following boot-time warning that showed up after merging the IO daisy chain rework: [ 3.849334] WARNING: at kernel/irq/manage.c:436 enable_irq+0x3c/0x78() [ 3.856231] Unbalanced enable for IRQ 297 [ 3.860473] Modules linked in: [ 3.863739] [<c001a114>] (unwind_backtrace+0x0/0xf0) from [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) [ 3.873687] [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) from [<c003c894>] (warn_slowpath_fmt+0x30/0x40) [ 3.883819] [<c003c894>] (warn_slowpath_fmt+0x30/0x40) from [<c00993e0>] (enable_irq+0x3c/0x78) [ 3.893035] [<c00993e0>] (enable_irq+0x3c/0x78) from [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) [ 3.902099] [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) from [<c067161c>] (init_machine_late+0x1c/0x28) [ 3.911773] [<c067161c>] (init_machine_late+0x1c/0x28) from [<c0008648>] (do_one_initcall+0x34/0x178) [ 3.921539] [<c0008648>] (do_one_initcall+0x34/0x178) from [<c066e8f4>] (kernel_init+0xfc/0x1c0) [ 3.930847] [<c066e8f4>] (kernel_init+0xfc/0x1c0) from [<c00140b0>] (kernel_thread_exit+0x0/0x8) [ 3.940246] ---[ end trace 55a0ad32ca2ca682 ]--- Reported-by: Javier Martinez Canillas <javier@dowhile0.org> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-29 14:03:34 +00:00
ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
if (!ret)
irq_set_status_flags(omap_prcm_event_to_irq("io"),
IRQ_NOAUTOEN);
}
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge commit 99b59df0 (ARM: OMAP3: PM: fix shared PRCM interrupt leave disabled at boot) added IRQ_NOAUTOEN to the PRCM interrupt so it could be enabled later if needed. However, this commit was partially undone when merging the IO daisy chain rework in 9a17d88e (Merge tag 'omap-devel-c-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-pm This patch adds back the IRQ_NOAUTOEN fix that was removed by the merge resolution. This also fixes the following boot-time warning that showed up after merging the IO daisy chain rework: [ 3.849334] WARNING: at kernel/irq/manage.c:436 enable_irq+0x3c/0x78() [ 3.856231] Unbalanced enable for IRQ 297 [ 3.860473] Modules linked in: [ 3.863739] [<c001a114>] (unwind_backtrace+0x0/0xf0) from [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) [ 3.873687] [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) from [<c003c894>] (warn_slowpath_fmt+0x30/0x40) [ 3.883819] [<c003c894>] (warn_slowpath_fmt+0x30/0x40) from [<c00993e0>] (enable_irq+0x3c/0x78) [ 3.893035] [<c00993e0>] (enable_irq+0x3c/0x78) from [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) [ 3.902099] [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) from [<c067161c>] (init_machine_late+0x1c/0x28) [ 3.911773] [<c067161c>] (init_machine_late+0x1c/0x28) from [<c0008648>] (do_one_initcall+0x34/0x178) [ 3.921539] [<c0008648>] (do_one_initcall+0x34/0x178) from [<c066e8f4>] (kernel_init+0xfc/0x1c0) [ 3.930847] [<c066e8f4>] (kernel_init+0xfc/0x1c0) from [<c00140b0>] (kernel_thread_exit+0x0/0x8) [ 3.940246] ---[ end trace 55a0ad32ca2ca682 ]--- Reported-by: Javier Martinez Canillas <javier@dowhile0.org> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-29 14:03:34 +00:00
return ret;
}
subsys_initcall(omap3xxx_prcm_init);