mirror of
https://github.com/freebsd/freebsd-src
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072a4ba82a
Sponsored by: Arm Ltd
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*
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* Double-precision vector sinh(x) function.
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*
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* Copyright (c) 2022-2023, Arm Limited.
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* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
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*/
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#include "v_math.h"
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#include "estrin.h"
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#include "pl_sig.h"
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#include "pl_test.h"
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#define AbsMask 0x7fffffffffffffff
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#define Half 0x3fe0000000000000
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#define BigBound \
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0x4080000000000000 /* 2^9. expm1 helper overflows for large input. */
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#define TinyBound \
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0x3e50000000000000 /* 2^-26, below which sinh(x) rounds to x. */
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#define InvLn2 v_f64 (0x1.71547652b82fep0)
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#define MLn2hi v_f64 (-0x1.62e42fefa39efp-1)
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#define MLn2lo v_f64 (-0x1.abc9e3b39803fp-56)
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#define Shift v_f64 (0x1.8p52)
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#define One 0x3ff0000000000000
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#define C(i) v_f64 (__expm1_poly[i])
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#if V_SUPPORTED
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static inline v_f64_t
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expm1_inline (v_f64_t x)
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{
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/* Reduce argument:
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exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
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where i = round(x / ln2)
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and f = x - i * ln2 (f in [-ln2/2, ln2/2]). */
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v_f64_t j = v_fma_f64 (InvLn2, x, Shift) - Shift;
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v_s64_t i = v_to_s64_f64 (j);
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v_f64_t f = v_fma_f64 (j, MLn2hi, x);
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f = v_fma_f64 (j, MLn2lo, f);
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/* Approximate expm1(f) using polynomial. */
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v_f64_t f2 = f * f, f4 = f2 * f2, f8 = f4 * f4;
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v_f64_t p = v_fma_f64 (f2, ESTRIN_10 (f, f2, f4, f8, C), f);
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/* t = 2^i. */
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v_f64_t t = v_as_f64_u64 (v_as_u64_s64 (i << 52) + One);
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/* expm1(x) ~= p * t + (t - 1). */
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return v_fma_f64 (p, t, t - 1);
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}
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static NOINLINE VPCS_ATTR v_f64_t
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special_case (v_f64_t x)
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{
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return v_call_f64 (sinh, x, x, v_u64 (-1));
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}
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/* Approximation for vector double-precision sinh(x) using expm1.
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sinh(x) = (exp(x) - exp(-x)) / 2.
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The greatest observed error is 2.57 ULP:
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sinh(0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
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want 0x1.ab34e59d678d9p-2. */
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VPCS_ATTR v_f64_t V_NAME (sinh) (v_f64_t x)
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{
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v_u64_t ix = v_as_u64_f64 (x);
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v_u64_t iax = ix & AbsMask;
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v_f64_t ax = v_as_f64_u64 (iax);
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v_u64_t sign = ix & ~AbsMask;
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v_f64_t halfsign = v_as_f64_u64 (sign | Half);
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#if WANT_SIMD_EXCEPT
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v_u64_t special = v_cond_u64 ((iax - TinyBound) >= (BigBound - TinyBound));
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#else
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v_u64_t special = v_cond_u64 (iax >= BigBound);
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#endif
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/* Fall back to scalar variant for all lanes if any of them are special. */
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if (unlikely (v_any_u64 (special)))
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return special_case (x);
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/* Up to the point that expm1 overflows, we can use it to calculate sinh
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using a slight rearrangement of the definition of sinh. This allows us to
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retain acceptable accuracy for very small inputs. */
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v_f64_t t = expm1_inline (ax);
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return (t + t / (t + 1)) * halfsign;
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}
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VPCS_ALIAS
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PL_SIG (V, D, 1, sinh, -10.0, 10.0)
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PL_TEST_ULP (V_NAME (sinh), 2.08)
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PL_TEST_EXPECT_FENV (V_NAME (sinh), WANT_SIMD_EXCEPT)
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PL_TEST_INTERVAL (V_NAME (sinh), 0, TinyBound, 1000)
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PL_TEST_INTERVAL (V_NAME (sinh), -0, -TinyBound, 1000)
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PL_TEST_INTERVAL (V_NAME (sinh), TinyBound, BigBound, 500000)
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PL_TEST_INTERVAL (V_NAME (sinh), -TinyBound, -BigBound, 500000)
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PL_TEST_INTERVAL (V_NAME (sinh), BigBound, inf, 1000)
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PL_TEST_INTERVAL (V_NAME (sinh), -BigBound, -inf, 1000)
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#endif
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