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https://github.com/freebsd/freebsd-src
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161 lines
4.8 KiB
C
161 lines
4.8 KiB
C
/*
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* Single-precision vector log(1+x) function.
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*
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* Copyright (c) 2022-2023, Arm Limited.
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* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
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*/
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#include "v_math.h"
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#include "pl_sig.h"
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#include "pl_test.h"
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#if V_SUPPORTED
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#define AbsMask 0x7fffffff
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#define TinyBound 0x340 /* asuint32(0x1p-23). ulp=0.5 at 0x1p-23. */
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#define MinusOne 0xbf800000
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#define Ln2 (0x1.62e43p-1f)
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#define Four 0x40800000
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#define ThreeQuarters v_u32 (0x3f400000)
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#define C(i) v_f32 (__log1pf_data.coeffs[i])
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static inline v_f32_t
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eval_poly (v_f32_t m)
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{
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#ifdef V_LOG1PF_1U3
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/* Approximate log(1+m) on [-0.25, 0.5] using Horner scheme. */
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v_f32_t p = v_fma_f32 (C (8), m, C (7));
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p = v_fma_f32 (p, m, C (6));
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p = v_fma_f32 (p, m, C (5));
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p = v_fma_f32 (p, m, C (4));
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p = v_fma_f32 (p, m, C (3));
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p = v_fma_f32 (p, m, C (2));
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p = v_fma_f32 (p, m, C (1));
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p = v_fma_f32 (p, m, C (0));
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return v_fma_f32 (m, m * p, m);
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#elif defined(V_LOG1PF_2U5)
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/* Approximate log(1+m) on [-0.25, 0.5] using Estrin scheme. */
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v_f32_t p_12 = v_fma_f32 (m, C (1), C (0));
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v_f32_t p_34 = v_fma_f32 (m, C (3), C (2));
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v_f32_t p_56 = v_fma_f32 (m, C (5), C (4));
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v_f32_t p_78 = v_fma_f32 (m, C (7), C (6));
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v_f32_t m2 = m * m;
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v_f32_t p_02 = v_fma_f32 (m2, p_12, m);
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v_f32_t p_36 = v_fma_f32 (m2, p_56, p_34);
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v_f32_t p_79 = v_fma_f32 (m2, C (8), p_78);
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v_f32_t m4 = m2 * m2;
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v_f32_t p_06 = v_fma_f32 (m4, p_36, p_02);
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return v_fma_f32 (m4, m4 * p_79, p_06);
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#else
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#error No precision specified for v_log1pf
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#endif
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}
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static inline float
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handle_special (float x)
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{
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uint32_t ix = asuint (x);
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uint32_t ia = ix & AbsMask;
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if (ix == 0xff800000 || ia > 0x7f800000 || ix > 0xbf800000)
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{
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/* x == -Inf => log1pf(x) = NaN.
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x < -1.0 => log1pf(x) = NaN.
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x == +/-NaN => log1pf(x) = NaN. */
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#if WANT_SIMD_EXCEPT
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return __math_invalidf (asfloat (ia));
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#else
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return NAN;
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#endif
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}
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if (ix == 0xbf800000)
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{
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/* x == -1.0 => log1pf(x) = -Inf. */
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#if WANT_SIMD_EXCEPT
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return __math_divzerof (ix);
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#else
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return -INFINITY;
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#endif
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}
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/* |x| < TinyBound => log1p(x) = x. */
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return x;
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}
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/* Vector log1pf approximation using polynomial on reduced interval. Accuracy is
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the same as for the scalar algorithm, i.e. worst-case error when using Estrin
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is roughly 2.02 ULP:
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log1pf(0x1.21e13ap-2) got 0x1.fe8028p-3 want 0x1.fe802cp-3. */
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VPCS_ATTR v_f32_t V_NAME (log1pf) (v_f32_t x)
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{
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v_u32_t ix = v_as_u32_f32 (x);
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v_u32_t ia12 = (ix >> 20) & v_u32 (0x7f8);
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v_u32_t special_cases
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= v_cond_u32 (ia12 - v_u32 (TinyBound) >= (0x7f8 - TinyBound))
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| v_cond_u32 (ix >= MinusOne);
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v_f32_t special_arg = x;
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#if WANT_SIMD_EXCEPT
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if (unlikely (v_any_u32 (special_cases)))
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/* Side-step special lanes so fenv exceptions are not triggered
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inadvertently. */
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x = v_sel_f32 (special_cases, v_f32 (1), x);
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#endif
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/* With x + 1 = t * 2^k (where t = m + 1 and k is chosen such that m
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is in [-0.25, 0.5]):
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log1p(x) = log(t) + log(2^k) = log1p(m) + k*log(2).
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We approximate log1p(m) with a polynomial, then scale by
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k*log(2). Instead of doing this directly, we use an intermediate
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scale factor s = 4*k*log(2) to ensure the scale is representable
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as a normalised fp32 number. */
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v_f32_t m = x + v_f32 (1.0f);
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/* Choose k to scale x to the range [-1/4, 1/2]. */
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v_s32_t k = (v_as_s32_f32 (m) - ThreeQuarters) & v_u32 (0xff800000);
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/* Scale x by exponent manipulation. */
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v_f32_t m_scale = v_as_f32_u32 (v_as_u32_f32 (x) - v_as_u32_s32 (k));
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/* Scale up to ensure that the scale factor is representable as normalised
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fp32 number, and scale m down accordingly. */
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v_f32_t s = v_as_f32_u32 (v_u32 (Four) - k);
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m_scale = m_scale + v_fma_f32 (v_f32 (0.25f), s, v_f32 (-1.0f));
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/* Evaluate polynomial on the reduced interval. */
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v_f32_t p = eval_poly (m_scale);
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/* The scale factor to be applied back at the end - by multiplying float(k)
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by 2^-23 we get the unbiased exponent of k. */
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v_f32_t scale_back = v_to_f32_s32 (k) * v_f32 (0x1p-23f);
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/* Apply the scaling back. */
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v_f32_t y = v_fma_f32 (scale_back, v_f32 (Ln2), p);
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if (unlikely (v_any_u32 (special_cases)))
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return v_call_f32 (handle_special, special_arg, y, special_cases);
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return y;
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}
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VPCS_ALIAS
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PL_SIG (V, F, 1, log1p, -0.9, 10.0)
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PL_TEST_ULP (V_NAME (log1pf), 1.53)
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PL_TEST_EXPECT_FENV (V_NAME (log1pf), WANT_SIMD_EXCEPT)
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PL_TEST_INTERVAL (V_NAME (log1pf), -10.0, 10.0, 10000)
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PL_TEST_INTERVAL (V_NAME (log1pf), 0.0, 0x1p-23, 30000)
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PL_TEST_INTERVAL (V_NAME (log1pf), 0x1p-23, 0.001, 50000)
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PL_TEST_INTERVAL (V_NAME (log1pf), 0.001, 1.0, 50000)
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PL_TEST_INTERVAL (V_NAME (log1pf), 0.0, -0x1p-23, 30000)
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PL_TEST_INTERVAL (V_NAME (log1pf), -0x1p-23, -0.001, 30000)
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PL_TEST_INTERVAL (V_NAME (log1pf), -0.001, -1.0, 50000)
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PL_TEST_INTERVAL (V_NAME (log1pf), -1.0, inf, 1000)
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#endif
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