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9bac70b851
ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status). |
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.. | ||
acphy.c | ||
acphyreg.h | ||
amphy.c | ||
amphyreg.h | ||
bmtphy.c | ||
bmtphyreg.h | ||
brgphy.c | ||
brgphyreg.h | ||
dcphy.c | ||
e1000phy.c | ||
e1000phyreg.h | ||
exphy.c | ||
inphy.c | ||
inphyreg.h | ||
lxtphy.c | ||
lxtphyreg.h | ||
mii.c | ||
mii.h | ||
mii_physubr.c | ||
miibus_if.m | ||
miidevs | ||
miivar.h | ||
mlphy.c | ||
nsgphy.c | ||
nsgphyreg.h | ||
nsphy.c | ||
nsphyreg.h | ||
pnaphy.c | ||
pnphy.c | ||
qsphy.c | ||
qsphyreg.h | ||
rgephy.c | ||
rgephyreg.h | ||
rlphy.c | ||
ruephy.c | ||
ruephyreg.h | ||
tdkphy.c | ||
tdkphyreg.h | ||
tlphy.c | ||
tlphyreg.h | ||
ukphy.c | ||
ukphy_subr.c | ||
xmphy.c | ||
xmphyreg.h |