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https://github.com/freebsd/freebsd-src
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56a26fc1af
Hide definitions of several functions that currently don't have implementatations in the arm64 vmm port. In particular, add a WITH_VMMAPI_SNAPSHOT preprocessor variable that can be used to enable compilation of save/restore functions, and conditionalize compilation of some functions only used by amd64 bhyve. If in the long term they remain amd64-only, they can move to vmmapi_machdep.c, but for now it's not clear to me that that's the right thing to do. MFC after: 2 weeks Sponsored by: Innovate UK
608 lines
14 KiB
C
608 lines
14 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <machine/specialreg.h>
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#include <machine/vmm.h>
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#include <machine/vmm_dev.h>
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#include <machine/vmm_snapshot.h>
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#include <string.h>
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#include "vmmapi.h"
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#include "internal.h"
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const char *vm_capstrmap[] = {
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[VM_CAP_HALT_EXIT] = "hlt_exit",
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[VM_CAP_MTRAP_EXIT] = "mtrap_exit",
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[VM_CAP_PAUSE_EXIT] = "pause_exit",
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[VM_CAP_UNRESTRICTED_GUEST] = "unrestricted_guest",
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[VM_CAP_ENABLE_INVPCID] = "enable_invpcid",
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[VM_CAP_BPT_EXIT] = "bpt_exit",
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[VM_CAP_RDPID] = "rdpid",
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[VM_CAP_RDTSCP] = "rdtscp",
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[VM_CAP_IPI_EXIT] = "ipi_exit",
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[VM_CAP_MASK_HWINTR] = "mask_hwintr",
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[VM_CAP_RFLAGS_TF] = "rflags_tf",
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[VM_CAP_MAX] = NULL,
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};
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#define VM_MD_IOCTLS \
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VM_SET_SEGMENT_DESCRIPTOR, \
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VM_GET_SEGMENT_DESCRIPTOR, \
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VM_SET_KERNEMU_DEV, \
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VM_GET_KERNEMU_DEV, \
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VM_LAPIC_IRQ, \
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VM_LAPIC_LOCAL_IRQ, \
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VM_LAPIC_MSI, \
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VM_IOAPIC_ASSERT_IRQ, \
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VM_IOAPIC_DEASSERT_IRQ, \
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VM_IOAPIC_PULSE_IRQ, \
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VM_IOAPIC_PINCOUNT, \
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VM_ISA_ASSERT_IRQ, \
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VM_ISA_DEASSERT_IRQ, \
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VM_ISA_PULSE_IRQ, \
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VM_ISA_SET_IRQ_TRIGGER, \
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VM_INJECT_NMI, \
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VM_SET_X2APIC_STATE, \
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VM_GET_X2APIC_STATE, \
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VM_GET_HPET_CAPABILITIES, \
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VM_RTC_WRITE, \
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VM_RTC_READ, \
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VM_RTC_SETTIME, \
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VM_RTC_GETTIME, \
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VM_GET_GPA_PMAP, \
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VM_GLA2GPA, \
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VM_SET_INTINFO, \
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VM_GET_INTINFO, \
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VM_RESTART_INSTRUCTION, \
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VM_SNAPSHOT_REQ, \
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VM_RESTORE_TIME
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const cap_ioctl_t vm_ioctl_cmds[] = {
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VM_COMMON_IOCTLS,
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VM_PPT_IOCTLS,
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VM_MD_IOCTLS,
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};
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size_t vm_ioctl_ncmds = nitems(vm_ioctl_cmds);
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int
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vm_set_desc(struct vcpu *vcpu, int reg,
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uint64_t base, uint32_t limit, uint32_t access)
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{
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int error;
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struct vm_seg_desc vmsegdesc;
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bzero(&vmsegdesc, sizeof(vmsegdesc));
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vmsegdesc.regnum = reg;
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vmsegdesc.desc.base = base;
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vmsegdesc.desc.limit = limit;
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vmsegdesc.desc.access = access;
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error = vcpu_ioctl(vcpu, VM_SET_SEGMENT_DESCRIPTOR, &vmsegdesc);
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return (error);
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}
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int
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vm_get_desc(struct vcpu *vcpu, int reg, uint64_t *base, uint32_t *limit,
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uint32_t *access)
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{
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int error;
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struct vm_seg_desc vmsegdesc;
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bzero(&vmsegdesc, sizeof(vmsegdesc));
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vmsegdesc.regnum = reg;
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error = vcpu_ioctl(vcpu, VM_GET_SEGMENT_DESCRIPTOR, &vmsegdesc);
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if (error == 0) {
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*base = vmsegdesc.desc.base;
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*limit = vmsegdesc.desc.limit;
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*access = vmsegdesc.desc.access;
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}
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return (error);
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}
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int
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vm_get_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *seg_desc)
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{
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int error;
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error = vm_get_desc(vcpu, reg, &seg_desc->base, &seg_desc->limit,
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&seg_desc->access);
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return (error);
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}
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int
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vm_lapic_irq(struct vcpu *vcpu, int vector)
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{
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struct vm_lapic_irq vmirq;
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bzero(&vmirq, sizeof(vmirq));
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vmirq.vector = vector;
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return (vcpu_ioctl(vcpu, VM_LAPIC_IRQ, &vmirq));
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}
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int
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vm_lapic_local_irq(struct vcpu *vcpu, int vector)
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{
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struct vm_lapic_irq vmirq;
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bzero(&vmirq, sizeof(vmirq));
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vmirq.vector = vector;
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return (vcpu_ioctl(vcpu, VM_LAPIC_LOCAL_IRQ, &vmirq));
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}
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int
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vm_lapic_msi(struct vmctx *ctx, uint64_t addr, uint64_t msg)
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{
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struct vm_lapic_msi vmmsi;
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bzero(&vmmsi, sizeof(vmmsi));
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vmmsi.addr = addr;
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vmmsi.msg = msg;
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return (ioctl(ctx->fd, VM_LAPIC_MSI, &vmmsi));
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}
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int
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vm_raise_msi(struct vmctx *ctx, uint64_t addr, uint64_t msg,
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int bus __unused, int slot __unused, int func __unused)
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{
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return (vm_lapic_msi(ctx, addr, msg));
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}
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int
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vm_apicid2vcpu(struct vmctx *ctx __unused, int apicid)
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{
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/*
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* The apic id associated with the 'vcpu' has the same numerical value
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* as the 'vcpu' itself.
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*/
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return (apicid);
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}
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int
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vm_ioapic_assert_irq(struct vmctx *ctx, int irq)
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{
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struct vm_ioapic_irq ioapic_irq;
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bzero(&ioapic_irq, sizeof(struct vm_ioapic_irq));
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ioapic_irq.irq = irq;
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return (ioctl(ctx->fd, VM_IOAPIC_ASSERT_IRQ, &ioapic_irq));
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}
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int
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vm_ioapic_deassert_irq(struct vmctx *ctx, int irq)
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{
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struct vm_ioapic_irq ioapic_irq;
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bzero(&ioapic_irq, sizeof(struct vm_ioapic_irq));
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ioapic_irq.irq = irq;
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return (ioctl(ctx->fd, VM_IOAPIC_DEASSERT_IRQ, &ioapic_irq));
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}
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int
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vm_ioapic_pulse_irq(struct vmctx *ctx, int irq)
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{
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struct vm_ioapic_irq ioapic_irq;
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bzero(&ioapic_irq, sizeof(struct vm_ioapic_irq));
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ioapic_irq.irq = irq;
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return (ioctl(ctx->fd, VM_IOAPIC_PULSE_IRQ, &ioapic_irq));
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}
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int
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vm_ioapic_pincount(struct vmctx *ctx, int *pincount)
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{
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return (ioctl(ctx->fd, VM_IOAPIC_PINCOUNT, pincount));
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}
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int
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vm_isa_assert_irq(struct vmctx *ctx, int atpic_irq, int ioapic_irq)
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{
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struct vm_isa_irq isa_irq;
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bzero(&isa_irq, sizeof(struct vm_isa_irq));
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isa_irq.atpic_irq = atpic_irq;
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isa_irq.ioapic_irq = ioapic_irq;
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return (ioctl(ctx->fd, VM_ISA_ASSERT_IRQ, &isa_irq));
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}
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int
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vm_isa_deassert_irq(struct vmctx *ctx, int atpic_irq, int ioapic_irq)
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{
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struct vm_isa_irq isa_irq;
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bzero(&isa_irq, sizeof(struct vm_isa_irq));
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isa_irq.atpic_irq = atpic_irq;
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isa_irq.ioapic_irq = ioapic_irq;
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return (ioctl(ctx->fd, VM_ISA_DEASSERT_IRQ, &isa_irq));
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}
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int
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vm_isa_pulse_irq(struct vmctx *ctx, int atpic_irq, int ioapic_irq)
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{
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struct vm_isa_irq isa_irq;
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bzero(&isa_irq, sizeof(struct vm_isa_irq));
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isa_irq.atpic_irq = atpic_irq;
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isa_irq.ioapic_irq = ioapic_irq;
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return (ioctl(ctx->fd, VM_ISA_PULSE_IRQ, &isa_irq));
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}
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int
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vm_isa_set_irq_trigger(struct vmctx *ctx, int atpic_irq,
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enum vm_intr_trigger trigger)
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{
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struct vm_isa_irq_trigger isa_irq_trigger;
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bzero(&isa_irq_trigger, sizeof(struct vm_isa_irq_trigger));
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isa_irq_trigger.atpic_irq = atpic_irq;
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isa_irq_trigger.trigger = trigger;
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return (ioctl(ctx->fd, VM_ISA_SET_IRQ_TRIGGER, &isa_irq_trigger));
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}
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int
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vm_inject_nmi(struct vcpu *vcpu)
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{
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struct vm_nmi vmnmi;
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bzero(&vmnmi, sizeof(vmnmi));
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return (vcpu_ioctl(vcpu, VM_INJECT_NMI, &vmnmi));
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}
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int
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vm_inject_exception(struct vcpu *vcpu, int vector, int errcode_valid,
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uint32_t errcode, int restart_instruction)
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{
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struct vm_exception exc;
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exc.vector = vector;
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exc.error_code = errcode;
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exc.error_code_valid = errcode_valid;
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exc.restart_instruction = restart_instruction;
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return (vcpu_ioctl(vcpu, VM_INJECT_EXCEPTION, &exc));
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}
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int
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vm_readwrite_kernemu_device(struct vcpu *vcpu, vm_paddr_t gpa,
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bool write, int size, uint64_t *value)
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{
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struct vm_readwrite_kernemu_device irp = {
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.access_width = fls(size) - 1,
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.gpa = gpa,
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.value = write ? *value : ~0ul,
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};
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long cmd = (write ? VM_SET_KERNEMU_DEV : VM_GET_KERNEMU_DEV);
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int rc;
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rc = vcpu_ioctl(vcpu, cmd, &irp);
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if (rc == 0 && !write)
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*value = irp.value;
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return (rc);
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}
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int
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vm_get_x2apic_state(struct vcpu *vcpu, enum x2apic_state *state)
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{
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int error;
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struct vm_x2apic x2apic;
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bzero(&x2apic, sizeof(x2apic));
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error = vcpu_ioctl(vcpu, VM_GET_X2APIC_STATE, &x2apic);
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*state = x2apic.state;
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return (error);
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}
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int
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vm_set_x2apic_state(struct vcpu *vcpu, enum x2apic_state state)
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{
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int error;
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struct vm_x2apic x2apic;
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bzero(&x2apic, sizeof(x2apic));
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x2apic.state = state;
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error = vcpu_ioctl(vcpu, VM_SET_X2APIC_STATE, &x2apic);
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return (error);
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}
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int
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vm_get_hpet_capabilities(struct vmctx *ctx, uint32_t *capabilities)
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{
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int error;
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struct vm_hpet_cap cap;
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bzero(&cap, sizeof(struct vm_hpet_cap));
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error = ioctl(ctx->fd, VM_GET_HPET_CAPABILITIES, &cap);
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if (capabilities != NULL)
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*capabilities = cap.capabilities;
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return (error);
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}
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int
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vm_rtc_write(struct vmctx *ctx, int offset, uint8_t value)
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{
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struct vm_rtc_data rtcdata;
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int error;
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bzero(&rtcdata, sizeof(struct vm_rtc_data));
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rtcdata.offset = offset;
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rtcdata.value = value;
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error = ioctl(ctx->fd, VM_RTC_WRITE, &rtcdata);
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return (error);
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}
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int
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vm_rtc_read(struct vmctx *ctx, int offset, uint8_t *retval)
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{
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struct vm_rtc_data rtcdata;
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int error;
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bzero(&rtcdata, sizeof(struct vm_rtc_data));
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rtcdata.offset = offset;
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error = ioctl(ctx->fd, VM_RTC_READ, &rtcdata);
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if (error == 0)
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*retval = rtcdata.value;
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return (error);
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}
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int
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vm_rtc_settime(struct vmctx *ctx, time_t secs)
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{
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struct vm_rtc_time rtctime;
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int error;
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bzero(&rtctime, sizeof(struct vm_rtc_time));
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rtctime.secs = secs;
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error = ioctl(ctx->fd, VM_RTC_SETTIME, &rtctime);
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return (error);
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}
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int
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vm_rtc_gettime(struct vmctx *ctx, time_t *secs)
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{
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struct vm_rtc_time rtctime;
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int error;
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bzero(&rtctime, sizeof(struct vm_rtc_time));
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error = ioctl(ctx->fd, VM_RTC_GETTIME, &rtctime);
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if (error == 0)
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*secs = rtctime.secs;
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return (error);
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}
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/*
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* From Intel Vol 3a:
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* Table 9-1. IA-32 Processor States Following Power-up, Reset or INIT
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*/
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int
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vcpu_reset(struct vcpu *vcpu)
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{
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int error;
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uint64_t rflags, rip, cr0, cr4, zero, desc_base, rdx;
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uint32_t desc_access, desc_limit;
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uint16_t sel;
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zero = 0;
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rflags = 0x2;
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error = vm_set_register(vcpu, VM_REG_GUEST_RFLAGS, rflags);
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if (error)
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goto done;
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rip = 0xfff0;
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if ((error = vm_set_register(vcpu, VM_REG_GUEST_RIP, rip)) != 0)
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goto done;
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/*
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* According to Intels Software Developer Manual CR0 should be
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* initialized with CR0_ET | CR0_NW | CR0_CD but that crashes some
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* guests like Windows.
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*/
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cr0 = CR0_NE;
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if ((error = vm_set_register(vcpu, VM_REG_GUEST_CR0, cr0)) != 0)
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goto done;
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if ((error = vm_set_register(vcpu, VM_REG_GUEST_CR2, zero)) != 0)
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goto done;
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if ((error = vm_set_register(vcpu, VM_REG_GUEST_CR3, zero)) != 0)
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goto done;
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cr4 = 0;
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if ((error = vm_set_register(vcpu, VM_REG_GUEST_CR4, cr4)) != 0)
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goto done;
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/*
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* CS: present, r/w, accessed, 16-bit, byte granularity, usable
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*/
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desc_base = 0xffff0000;
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desc_limit = 0xffff;
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desc_access = 0x0093;
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error = vm_set_desc(vcpu, VM_REG_GUEST_CS,
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desc_base, desc_limit, desc_access);
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if (error)
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goto done;
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sel = 0xf000;
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if ((error = vm_set_register(vcpu, VM_REG_GUEST_CS, sel)) != 0)
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goto done;
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/*
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* SS,DS,ES,FS,GS: present, r/w, accessed, 16-bit, byte granularity
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*/
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desc_base = 0;
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desc_limit = 0xffff;
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desc_access = 0x0093;
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error = vm_set_desc(vcpu, VM_REG_GUEST_SS,
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desc_base, desc_limit, desc_access);
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if (error)
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goto done;
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error = vm_set_desc(vcpu, VM_REG_GUEST_DS,
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desc_base, desc_limit, desc_access);
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if (error)
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goto done;
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error = vm_set_desc(vcpu, VM_REG_GUEST_ES,
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desc_base, desc_limit, desc_access);
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if (error)
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goto done;
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error = vm_set_desc(vcpu, VM_REG_GUEST_FS,
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desc_base, desc_limit, desc_access);
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if (error)
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goto done;
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|
|
error = vm_set_desc(vcpu, VM_REG_GUEST_GS,
|
|
desc_base, desc_limit, desc_access);
|
|
if (error)
|
|
goto done;
|
|
|
|
sel = 0;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_SS, sel)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_DS, sel)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_ES, sel)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_FS, sel)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_GS, sel)) != 0)
|
|
goto done;
|
|
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_EFER, zero)) != 0)
|
|
goto done;
|
|
|
|
/* General purpose registers */
|
|
rdx = 0xf00;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RAX, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RBX, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RCX, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RDX, rdx)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RSI, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RDI, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RBP, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_RSP, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R8, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R9, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R10, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R11, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R12, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R13, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R14, zero)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_R15, zero)) != 0)
|
|
goto done;
|
|
|
|
/* GDTR, IDTR */
|
|
desc_base = 0;
|
|
desc_limit = 0xffff;
|
|
desc_access = 0;
|
|
error = vm_set_desc(vcpu, VM_REG_GUEST_GDTR,
|
|
desc_base, desc_limit, desc_access);
|
|
if (error != 0)
|
|
goto done;
|
|
|
|
error = vm_set_desc(vcpu, VM_REG_GUEST_IDTR,
|
|
desc_base, desc_limit, desc_access);
|
|
if (error != 0)
|
|
goto done;
|
|
|
|
/* TR */
|
|
desc_base = 0;
|
|
desc_limit = 0xffff;
|
|
desc_access = 0x0000008b;
|
|
error = vm_set_desc(vcpu, VM_REG_GUEST_TR, 0, 0, desc_access);
|
|
if (error)
|
|
goto done;
|
|
|
|
sel = 0;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_TR, sel)) != 0)
|
|
goto done;
|
|
|
|
/* LDTR */
|
|
desc_base = 0;
|
|
desc_limit = 0xffff;
|
|
desc_access = 0x00000082;
|
|
error = vm_set_desc(vcpu, VM_REG_GUEST_LDTR, desc_base,
|
|
desc_limit, desc_access);
|
|
if (error)
|
|
goto done;
|
|
|
|
sel = 0;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_LDTR, 0)) != 0)
|
|
goto done;
|
|
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_DR6,
|
|
0xffff0ff0)) != 0)
|
|
goto done;
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_DR7, 0x400)) !=
|
|
0)
|
|
goto done;
|
|
|
|
if ((error = vm_set_register(vcpu, VM_REG_GUEST_INTR_SHADOW,
|
|
zero)) != 0)
|
|
goto done;
|
|
|
|
error = 0;
|
|
done:
|
|
return (error);
|
|
}
|