Jung-uk Kim cd45fec044 Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta ... CPUs. These CPUs need explicit MSR configuration to expose ceratin CPU capabilities (e.g., CMPXCHG8B) to work around compatibility issues with ancient software. Unfortunately, Rise mP6 does not set the CX8 bit in CPUID and there is no MSR to expose the feature although all mP6 processors are capable of CMPXCHG8B according to datasheets I found from the Net. Clean up and simplify VIA PadLock detection while I am in the neighborhood.		2011-03-26 02:02:07 +00:00
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acpica	MFamd64: (based on) r209957	2010-11-12 20:55:14 +00:00
bios	Add compat shim for apm(4) to translate APM BIOS function numbers from i386	2010-11-11 19:20:33 +00:00
compile
conf	For now remove options FLOWTABLE from the remaining GENERIC kernel	2011-03-19 15:50:34 +00:00
i386	Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta	2011-03-26 02:02:07 +00:00
ibcs2	Extend struct sysvec with new method sv_schedtail, which is used for an	2011-03-08 19:01:45 +00:00
include	Modestly increase the maximum allowed size of the kmem map on i386.	2011-03-23 16:38:29 +00:00
isa	Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq because	2011-03-10 20:02:58 +00:00
linux	Enable shared page use for amd64/linux32 and i386/linux binaries.	2011-03-13 14:58:02 +00:00
pci	Add device IDs for two more ServerWorks Host-PCI bridges so that we can	2010-11-25 15:42:33 +00:00
svr4	Change some movl's to mov's. Newer GAS no longer accept 'movl' instructions	2009-01-31 11:37:21 +00:00
xbox	Update d_mmap() to accept vm_ooffset_t and vm_memattr_t.	2009-12-29 21:51:28 +00:00
xen	Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.	2011-01-21 10:26:26 +00:00
Makefile	Update entries for building tags.	2007-05-13 18:21:54 +00:00