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426 lines
9.4 KiB
C
426 lines
9.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2008 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/smp.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
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#include <machine/intr_machdep.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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#include <machine/trap.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/ofw_machdep.h>
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void *ap_pcpu;
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static register_t bsp_state[8] __aligned(8);
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static void cpudep_save_config(void *dummy);
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SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL);
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void
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cpudep_ap_early_bootstrap(void)
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{
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#ifndef __powerpc64__
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register_t reg;
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#endif
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switch (mfpvr() >> 16) {
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case IBM970:
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case IBM970FX:
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case IBM970MP:
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/* Set HIOR to 0 */
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__asm __volatile("mtspr 311,%0" :: "r"(0));
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powerpc_sync();
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/* Restore HID4 and HID5, which are necessary for the MMU */
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#ifdef __powerpc64__
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mtspr(SPR_HID4, bsp_state[2]); powerpc_sync(); isync();
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mtspr(SPR_HID5, bsp_state[3]); powerpc_sync(); isync();
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#else
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__asm __volatile("ld %0, 16(%2); sync; isync; \
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mtspr %1, %0; sync; isync;"
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: "=r"(reg) : "K"(SPR_HID4), "b"(bsp_state));
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__asm __volatile("ld %0, 24(%2); sync; isync; \
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mtspr %1, %0; sync; isync;"
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: "=r"(reg) : "K"(SPR_HID5), "b"(bsp_state));
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#endif
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powerpc_sync();
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break;
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case IBMPOWER8:
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case IBMPOWER8E:
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case IBMPOWER8NVL:
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case IBMPOWER9:
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#ifdef __powerpc64__
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if (mfmsr() & PSL_HV) {
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isync();
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/*
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* Direct interrupts to SRR instead of HSRR and
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* reset LPCR otherwise
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*/
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mtspr(SPR_LPID, 0);
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isync();
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mtspr(SPR_LPCR, lpcr);
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isync();
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/*
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* Nuke FSCR, to be managed on a per-process basis
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* later.
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*/
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mtspr(SPR_FSCR, 0);
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}
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#endif
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break;
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}
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__asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
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powerpc_sync();
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}
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uintptr_t
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cpudep_ap_bootstrap(void)
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{
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register_t msr, sp;
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msr = psl_kernset & ~PSL_EE;
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mtmsr(msr);
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pcpup->pc_curthread = pcpup->pc_idlethread;
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#ifdef __powerpc64__
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__asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread));
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#else
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__asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread));
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#endif
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pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
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sp = pcpup->pc_curpcb->pcb_sp;
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schedinit_ap();
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return (sp);
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}
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static register_t
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mpc74xx_l2_enable(register_t l2cr_config)
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{
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register_t ccr, bit;
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uint16_t vers;
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vers = mfpvr() >> 16;
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switch (vers) {
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case MPC7400:
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case MPC7410:
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bit = L2CR_L2IP;
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break;
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default:
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bit = L2CR_L2I;
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break;
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}
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ccr = mfspr(SPR_L2CR);
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if (ccr & L2CR_L2E)
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return (ccr);
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/* Configure L2 cache. */
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ccr = l2cr_config & ~L2CR_L2E;
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mtspr(SPR_L2CR, ccr | L2CR_L2I);
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do {
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ccr = mfspr(SPR_L2CR);
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} while (ccr & bit);
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powerpc_sync();
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mtspr(SPR_L2CR, l2cr_config);
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powerpc_sync();
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return (l2cr_config);
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}
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static register_t
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mpc745x_l3_enable(register_t l3cr_config)
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{
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register_t ccr;
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ccr = mfspr(SPR_L3CR);
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if (ccr & L3CR_L3E)
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return (ccr);
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/* Configure L3 cache. */
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ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN);
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mtspr(SPR_L3CR, ccr);
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ccr |= 0x4000000; /* Magic, but documented. */
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mtspr(SPR_L3CR, ccr);
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ccr |= L3CR_L3CLKEN;
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mtspr(SPR_L3CR, ccr);
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mtspr(SPR_L3CR, ccr | L3CR_L3I);
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while (mfspr(SPR_L3CR) & L3CR_L3I)
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;
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mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN);
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powerpc_sync();
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DELAY(100);
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mtspr(SPR_L3CR, ccr);
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powerpc_sync();
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DELAY(100);
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ccr |= L3CR_L3E;
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mtspr(SPR_L3CR, ccr);
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powerpc_sync();
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return(ccr);
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}
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static register_t
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mpc74xx_l1d_enable(void)
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{
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register_t hid;
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hid = mfspr(SPR_HID0);
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if (hid & HID0_DCE)
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return (hid);
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/* Enable L1 D-cache */
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hid |= HID0_DCE;
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powerpc_sync();
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mtspr(SPR_HID0, hid | HID0_DCFI);
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powerpc_sync();
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return (hid);
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}
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static register_t
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mpc74xx_l1i_enable(void)
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{
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register_t hid;
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hid = mfspr(SPR_HID0);
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if (hid & HID0_ICE)
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return (hid);
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/* Enable L1 I-cache */
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hid |= HID0_ICE;
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isync();
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mtspr(SPR_HID0, hid | HID0_ICFI);
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isync();
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return (hid);
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}
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static void
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cpudep_save_config(void *dummy)
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{
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uint16_t vers;
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vers = mfpvr() >> 16;
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switch(vers) {
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case IBM970:
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case IBM970FX:
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case IBM970MP:
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#ifdef __powerpc64__
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bsp_state[0] = mfspr(SPR_HID0);
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bsp_state[1] = mfspr(SPR_HID1);
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bsp_state[2] = mfspr(SPR_HID4);
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bsp_state[3] = mfspr(SPR_HID5);
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#else
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__asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
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: "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0));
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__asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
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: "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1));
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__asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
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: "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4));
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__asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
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: "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));
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#endif
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powerpc_sync();
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break;
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case IBMCELLBE:
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#ifdef NOTYET /* Causes problems if in instruction stream on 970 */
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if (mfmsr() & PSL_HV) {
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bsp_state[0] = mfspr(SPR_HID0);
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bsp_state[1] = mfspr(SPR_HID1);
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bsp_state[2] = mfspr(SPR_HID4);
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bsp_state[3] = mfspr(SPR_HID6);
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bsp_state[4] = mfspr(SPR_CELL_TSCR);
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}
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#endif
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bsp_state[5] = mfspr(SPR_CELL_TSRL);
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break;
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case MPC7450:
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case MPC7455:
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case MPC7457:
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/* Only MPC745x CPUs have an L3 cache. */
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bsp_state[3] = mfspr(SPR_L3CR);
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/* Fallthrough */
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case MPC7400:
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case MPC7410:
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case MPC7447A:
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case MPC7448:
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bsp_state[2] = mfspr(SPR_L2CR);
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bsp_state[1] = mfspr(SPR_HID1);
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bsp_state[0] = mfspr(SPR_HID0);
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break;
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}
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}
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void
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cpudep_ap_setup(void)
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{
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#ifndef __powerpc64__
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register_t reg;
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#endif
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uint16_t vers;
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vers = mfpvr() >> 16;
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switch(vers) {
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case IBM970:
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case IBM970FX:
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case IBM970MP:
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/*
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* The 970 has strange rules about how to update HID registers.
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* See Table 2-3, 970MP manual
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*
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* Note: HID4 and HID5 restored already in
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* cpudep_ap_early_bootstrap()
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*/
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__asm __volatile("mtasr %0; sync" :: "r"(0));
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#ifdef __powerpc64__
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__asm __volatile(" \
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sync; isync; \
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mtspr %1, %0; \
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mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
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mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
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sync; isync"
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:: "r"(bsp_state[0]), "K"(SPR_HID0));
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__asm __volatile("sync; isync; \
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mtspr %1, %0; mtspr %1, %0; sync; isync"
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:: "r"(bsp_state[1]), "K"(SPR_HID1));
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#else
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__asm __volatile(" \
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ld %0,0(%2); \
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sync; isync; \
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mtspr %1, %0; \
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mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
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mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
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sync; isync"
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: "=r"(reg) : "K"(SPR_HID0), "b"(bsp_state));
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__asm __volatile("ld %0, 8(%2); sync; isync; \
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mtspr %1, %0; mtspr %1, %0; sync; isync"
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: "=r"(reg) : "K"(SPR_HID1), "b"(bsp_state));
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#endif
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powerpc_sync();
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break;
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case IBMCELLBE:
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#ifdef NOTYET /* Causes problems if in instruction stream on 970 */
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if (mfmsr() & PSL_HV) {
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mtspr(SPR_HID0, bsp_state[0]);
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mtspr(SPR_HID1, bsp_state[1]);
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mtspr(SPR_HID4, bsp_state[2]);
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mtspr(SPR_HID6, bsp_state[3]);
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mtspr(SPR_CELL_TSCR, bsp_state[4]);
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}
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#endif
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mtspr(SPR_CELL_TSRL, bsp_state[5]);
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break;
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case MPC7400:
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case MPC7410:
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case MPC7447A:
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case MPC7448:
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case MPC7450:
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case MPC7455:
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case MPC7457:
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/* XXX: Program the CPU ID into PIR */
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__asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
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powerpc_sync();
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isync();
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mtspr(SPR_HID0, bsp_state[0]); isync();
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mtspr(SPR_HID1, bsp_state[1]); isync();
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/* Now enable the L3 cache. */
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switch (vers) {
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case MPC7450:
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case MPC7455:
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case MPC7457:
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/* Only MPC745x CPUs have an L3 cache. */
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mpc745x_l3_enable(bsp_state[3]);
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default:
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break;
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}
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mpc74xx_l2_enable(bsp_state[2]);
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mpc74xx_l1d_enable();
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mpc74xx_l1i_enable();
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break;
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case IBMPOWER7:
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case IBMPOWER7PLUS:
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case IBMPOWER8:
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case IBMPOWER8E:
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case IBMPOWER8NVL:
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case IBMPOWER9:
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#ifdef __powerpc64__
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if (mfmsr() & PSL_HV) {
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mtspr(SPR_LPCR, mfspr(SPR_LPCR) | lpcr |
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LPCR_PECE_WAKESET);
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isync();
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}
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#endif
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break;
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default:
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#ifdef __powerpc64__
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if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */
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break;
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#endif
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printf("WARNING: Unknown CPU type. Cache performace may be "
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"suboptimal.\n");
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break;
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}
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}
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