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https://github.com/freebsd/freebsd-src
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1587a9db92
This commit changes the API of pci_cfgreg(read|write) to add a domain argument (referred to as a segment in ACPI parlance) (note that this is not the same as a NUMA domain, but something PCI-specific). This does not yet enable access to domains other than 0, but updates the API to support domains. Places that use hard-coded bus/slot/function addresses have been updated to hardcode a domain of 0. A few places that have the PCI domain (segment) available such as the acpi_pcib_acpi.c Host-PCI bridge driver pass the PCI domain. The hpt27xx(4) and hptnr(4) drivers fail to attach to a device not on domain 0 since they provide APIs to their binary blobs that only permit bus/slot/function addressing. The x86 non-ACPI PCI bus drivers all hardcode a domain of 0 as they do not support multiple domains. Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D42827
323 lines
9.2 KiB
C
323 lines
9.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2018 Johannes Lundberg
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/tslog.h>
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#include <vm/vm.h>
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/* XXX: enable this once the KPI is available */
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/* #include <x86/physmem.h> */
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#include <machine/pci_cfgreg.h>
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#include <machine/md_var.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/pci/pci_early_quirks.h>
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#define MiB(v) ((unsigned long)(v) << 20)
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struct pci_device_id {
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uint32_t vendor;
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uint32_t device;
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const struct intel_stolen_ops *data;
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};
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/*
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* These global variables are read by LinuxKPI.
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* LinuxKPI provide this information to the i915 driver.
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*/
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vm_paddr_t intel_graphics_stolen_base = 0;
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vm_paddr_t intel_graphics_stolen_size = 0;
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SYSCTL_U64(_hw, OID_AUTO, intel_graphics_stolen_base, CTLFLAG_RD,
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&intel_graphics_stolen_base, 0,
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"Base address of the intel graphics stolen memory.");
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SYSCTL_U64(_hw, OID_AUTO, intel_graphics_stolen_size, CTLFLAG_RD,
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&intel_graphics_stolen_size, 0,
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"Size of the intel graphics stolen memory.");
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/*
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* Intel early quirks functions
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*/
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static vm_paddr_t
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intel_stolen_base_gen3(int domain, int bus, int slot, int func)
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{
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uint32_t ctrl;
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vm_paddr_t val;
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ctrl = pci_cfgregread(domain, bus, slot, func, INTEL_BSM, 4);
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val = ctrl & INTEL_BSM_MASK;
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return (val);
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}
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static vm_paddr_t
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intel_stolen_base_gen11(int domain, int bus, int slot, int func)
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{
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uint32_t ctrl;
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vm_paddr_t val;
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ctrl = pci_cfgregread(domain, bus, slot, func, INTEL_GEN11_BSM_DW0, 4);
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val = ctrl & INTEL_BSM_MASK;
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val |= (uint64_t)pci_cfgregread(
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domain, bus, slot, func, INTEL_GEN11_BSM_DW1, 4) << 32;
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return (val);
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}
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static vm_paddr_t
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intel_stolen_size_gen3(int domain, int bus, int slot, int func)
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{
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uint32_t ctrl;
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vm_paddr_t val;
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ctrl = pci_cfgregread(0, 0, 0, 0, I830_GMCH_CTRL, 2);
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val = ctrl & I855_GMCH_GMS_MASK;
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switch (val) {
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case I855_GMCH_GMS_STOLEN_1M:
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return (MiB(1));
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case I855_GMCH_GMS_STOLEN_4M:
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return (MiB(4));
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case I855_GMCH_GMS_STOLEN_8M:
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return (MiB(8));
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case I855_GMCH_GMS_STOLEN_16M:
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return (MiB(16));
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case I855_GMCH_GMS_STOLEN_32M:
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return (MiB(32));
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case I915_GMCH_GMS_STOLEN_48M:
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return (MiB(48));
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case I915_GMCH_GMS_STOLEN_64M:
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return (MiB(64));
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case G33_GMCH_GMS_STOLEN_128M:
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return (MiB(128));
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case G33_GMCH_GMS_STOLEN_256M:
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return (MiB(256));
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case INTEL_GMCH_GMS_STOLEN_96M:
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return (MiB(96));
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case INTEL_GMCH_GMS_STOLEN_160M:
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return (MiB(160));
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case INTEL_GMCH_GMS_STOLEN_224M:
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return (MiB(224));
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case INTEL_GMCH_GMS_STOLEN_352M:
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return (MiB(352));
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}
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return (0);
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}
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static vm_paddr_t
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intel_stolen_size_gen6(int domain, int bus, int slot, int func)
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{
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uint32_t ctrl;
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vm_paddr_t val;
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ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
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val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
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return (val * MiB(32));
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}
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static vm_paddr_t
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intel_stolen_size_gen8(int domain, int bus, int slot, int func)
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{
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uint32_t ctrl;
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vm_paddr_t val;
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ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
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val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
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return (val * MiB(32));
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}
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static vm_paddr_t
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intel_stolen_size_chv(int domain, int bus, int slot, int func)
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{
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uint32_t ctrl;
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vm_paddr_t val;
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ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
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val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
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/*
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* 0x0 to 0x10: 32MB increments starting at 0MB
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* 0x11 to 0x16: 4MB increments starting at 8MB
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* 0x17 to 0x1d: 4MB increments start at 36MB
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*/
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if (val < 0x11)
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return (val * MiB(32));
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else if (val < 0x17)
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return ((val - 0x11) * MiB(4) + MiB(8));
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else
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return ((val - 0x17) * MiB(4) + MiB(36));
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}
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static vm_paddr_t
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intel_stolen_size_gen9(int domain, int bus, int slot, int func)
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{
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uint32_t ctrl;
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vm_paddr_t val;
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ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
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val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
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/* 0x0 to 0xEF: 32MB increments starting at 0MB */
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/* 0xF0 to 0xFE: 4MB increments starting at 4MB */
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if (val < 0xF0)
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return (val * MiB(32));
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return ((val - 0xF0) * MiB(4) + MiB(4));
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}
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struct intel_stolen_ops {
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vm_paddr_t (*base)(int domain, int bus, int slot, int func);
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vm_paddr_t (*size)(int domain, int bus, int slot, int func);
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};
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static const struct intel_stolen_ops intel_stolen_ops_gen3 = {
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.base = intel_stolen_base_gen3,
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.size = intel_stolen_size_gen3,
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};
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static const struct intel_stolen_ops intel_stolen_ops_gen6 = {
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.base = intel_stolen_base_gen3,
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.size = intel_stolen_size_gen6,
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};
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static const struct intel_stolen_ops intel_stolen_ops_gen8 = {
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.base = intel_stolen_base_gen3,
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.size = intel_stolen_size_gen8,
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};
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static const struct intel_stolen_ops intel_stolen_ops_gen9 = {
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.base = intel_stolen_base_gen3,
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.size = intel_stolen_size_gen9,
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};
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static const struct intel_stolen_ops intel_stolen_ops_chv = {
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.base = intel_stolen_base_gen3,
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.size = intel_stolen_size_chv,
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};
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static const struct intel_stolen_ops intel_stolen_ops_gen11 = {
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.base = intel_stolen_base_gen11,
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.size = intel_stolen_size_gen9,
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};
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static const struct pci_device_id intel_ids[] = {
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INTEL_I915G_IDS(&intel_stolen_ops_gen3),
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INTEL_I915GM_IDS(&intel_stolen_ops_gen3),
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INTEL_I945G_IDS(&intel_stolen_ops_gen3),
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INTEL_I945GM_IDS(&intel_stolen_ops_gen3),
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INTEL_VLV_IDS(&intel_stolen_ops_gen6),
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INTEL_PINEVIEW_IDS(&intel_stolen_ops_gen3),
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INTEL_I965G_IDS(&intel_stolen_ops_gen3),
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INTEL_G33_IDS(&intel_stolen_ops_gen3),
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INTEL_I965GM_IDS(&intel_stolen_ops_gen3),
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INTEL_GM45_IDS(&intel_stolen_ops_gen3),
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INTEL_G45_IDS(&intel_stolen_ops_gen3),
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INTEL_IRONLAKE_D_IDS(&intel_stolen_ops_gen3),
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INTEL_IRONLAKE_M_IDS(&intel_stolen_ops_gen3),
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INTEL_SNB_D_IDS(&intel_stolen_ops_gen6),
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INTEL_SNB_M_IDS(&intel_stolen_ops_gen6),
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INTEL_IVB_M_IDS(&intel_stolen_ops_gen6),
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INTEL_IVB_D_IDS(&intel_stolen_ops_gen6),
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INTEL_HSW_IDS(&intel_stolen_ops_gen6),
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INTEL_BDW_IDS(&intel_stolen_ops_gen8),
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INTEL_CHV_IDS(&intel_stolen_ops_chv),
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INTEL_SKL_IDS(&intel_stolen_ops_gen9),
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INTEL_BXT_IDS(&intel_stolen_ops_gen9),
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INTEL_KBL_IDS(&intel_stolen_ops_gen9),
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INTEL_CFL_IDS(&intel_stolen_ops_gen9),
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INTEL_GLK_IDS(&intel_stolen_ops_gen9),
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INTEL_CNL_IDS(&intel_stolen_ops_gen9),
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INTEL_ICL_11_IDS(&intel_stolen_ops_gen11),
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INTEL_EHL_IDS(&intel_stolen_ops_gen11),
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INTEL_JSL_IDS(&intel_stolen_ops_gen11),
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INTEL_TGL_12_IDS(&intel_stolen_ops_gen11),
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INTEL_RKL_IDS(&intel_stolen_ops_gen11),
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INTEL_ADLS_IDS(&intel_stolen_ops_gen11),
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INTEL_ADLP_IDS(&intel_stolen_ops_gen11),
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INTEL_RPLS_IDS(&intel_stolen_ops_gen11),
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};
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/*
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* Buggy BIOS don't reserve memory for the GPU properly and the OS
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* can claim it before the GPU driver is loaded. This function will
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* check the registers for base and size of this memory and reserve
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* it for the GPU driver.
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* gen3 (2004) and newer devices are supported. Support for older hw
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* can be ported from Linux if needed.
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*/
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static void
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intel_graphics_stolen(void)
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{
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const struct intel_stolen_ops *ops;
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uint32_t vendor, device, class;
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int i;
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/* XXX: Scan bus instead of assuming 0:0:2:0? */
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const int domain = 0;
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const int bus = 0;
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const int slot = 2;
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const int func = 0;
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if (pci_cfgregopen() == 0)
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return;
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vendor = pci_cfgregread(domain, bus, slot, func, PCIR_VENDOR, 2);
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if (vendor != PCI_VENDOR_INTEL)
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return;
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class = pci_cfgregread(domain, bus, slot, func, PCIR_SUBCLASS, 2);
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if (class != PCI_CLASS_VGA)
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return;
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device = pci_cfgregread(domain, bus, slot, func, PCIR_DEVICE, 2);
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if (device == 0xFFFF)
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return;
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for (i = 0; i < nitems(intel_ids); i++) {
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if (intel_ids[i].device != device)
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continue;
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ops = intel_ids[i].data;
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intel_graphics_stolen_base = ops->base(domain, bus, slot, func);
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intel_graphics_stolen_size = ops->size(domain, bus, slot, func);
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break;
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}
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/* XXX: enable this once the KPI is available */
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/* phys_avail_reserve(intel_graphics_stolen_base, */
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/* intel_graphics_stolen_base + intel_graphics_stolen_size); */
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}
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void
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pci_early_quirks(void)
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{
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TSENTER();
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intel_graphics_stolen();
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TSEXIT();
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}
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