freebsd-src/sys/riscv
Mitchell Horne 5d6d627897 jh7110: Add StarFive JH7110 clock/reset generator drivers
Implement a core clknode driver for the JH7110 (StarFive VisionFive v2)
platform.

Add clock/reset generator drivers for the PLL, SYS, and AON clock
groupings.

Co-authored-by:	mhorne
Reviewed by:	mhorne
Sponsored by:	The FreeBSD Foundation (mhorne's contributions)
Differential Revision:	https://reviews.freebsd.org/D43037
2024-05-07 13:02:57 -03:00
..
allwinner sys: Remove $FreeBSD$: one-line sh pattern 2023-08-16 11:54:58 -06:00
conf sys/*/conf: do not use "../../conf/" when including std.* 2024-04-23 15:13:31 -06:00
include riscv: Convert local interrupt controller to a newbus PIC 2024-01-24 23:49:54 +00:00
riscv busdma: better handling of small segment bouncing 2024-05-07 13:02:57 -03:00
sifive hwreset: Move reset code in dev/hwreset 2024-01-10 19:20:28 +01:00
starfive jh7110: Add StarFive JH7110 clock/reset generator drivers 2024-05-07 13:02:57 -03:00