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264 lines
7.3 KiB
C
264 lines
7.3 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* BSD LICENSE
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*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copy
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the distribution.
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* 3. Neither the name of AMD corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Contact Information :
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* Rajesh Kumar <rajesh1.kumar@amd.com>
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*/
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#ifndef NTB_HW_AMD_H
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#define NTB_HW_AMD_H
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#define NTB_HW_AMD_VENDOR_ID 0x1022
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#define NTB_HW_AMD_DEVICE_ID1 0x145B
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#define NTB_HW_AMD_DEVICE_ID2 0x148B
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#define NTB_HW_HYGON_VENDOR_ID 0x19D4
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#define NTB_HW_HYGON_DEVICE_ID1 0x145B
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#define NTB_DEF_PEER_CNT 1
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#define NTB_DEF_PEER_IDX 0
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#define BIT(n) (1 << n)
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#define AMD_LINK_HB_TIMEOUT (1 * hz)
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#define NTB_LIN_STA_ACTIVE_BIT 0x00000002
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#define NTB_LNK_STA_SPEED_MASK 0x000F0000
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#define NTB_LNK_STA_WIDTH_MASK 0x03F00000
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#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LIN_STA_ACTIVE_BIT))
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#define NTB_LNK_STA_SPEED(x) (((x) & NTB_LNK_STA_SPEED_MASK) >> 16)
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#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20)
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#define amd_ntb_bar_read(SIZE, bar, offset) \
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bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
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ntb->bar_info[(bar)].pci_bus_handle, (offset))
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#define amd_ntb_bar_write(SIZE, bar, offset, val) \
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bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
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ntb->bar_info[(bar)].pci_bus_handle, (offset), (val))
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#define amd_ntb_reg_read(SIZE, offset) \
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amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset)
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#define amd_ntb_reg_write(SIZE, offset, val) \
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amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val)
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#define amd_ntb_peer_reg_read(SIZE, offset) \
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amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET)
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#define amd_ntb_peer_reg_write(SIZE, offset, val) \
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amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET, val)
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#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock)
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#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock)
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#define DB_MASK_ASSERT(sc, f) mtx_assert(&(sc)->db_mask_lock, (f))
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#define QUIRK_MW0_32BIT 0x01
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/* amd_ntb_conn_type are hardware numbers, cannot change. */
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enum amd_ntb_conn_type {
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NTB_CONN_NONE = -1,
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NTB_CONN_PRI,
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NTB_CONN_SEC,
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};
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enum ntb_default_port {
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NTB_PORT_PRI_USD,
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NTB_PORT_SEC_DSD
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};
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enum amd_ntb_bar {
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NTB_CONFIG_BAR = 0,
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NTB_BAR_1,
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NTB_BAR_2,
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NTB_BAR_3,
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NTB_MAX_BARS
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};
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struct amd_ntb_hw_info {
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t mw_count;
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uint8_t bar_start_idx;
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uint8_t spad_count;
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uint8_t db_count;
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uint8_t msix_vector_count;
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uint8_t quirks;
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char *desc;
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};
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struct amd_ntb_pci_bar_info {
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bus_space_tag_t pci_bus_tag;
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bus_space_handle_t pci_bus_handle;
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struct resource *pci_resource;
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vm_paddr_t pbase;
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caddr_t vbase;
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vm_size_t size;
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vm_memattr_t map_mode;
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int pci_resource_id;
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/* Configuration register offsets */
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uint32_t xlat_off;
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uint32_t limit_off;
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};
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struct amd_ntb_int_info {
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struct resource *res;
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void *tag;
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int rid;
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};
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struct amd_ntb_vec {
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struct amd_ntb_softc *ntb;
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uint32_t num;
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unsigned masked;
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};
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enum {
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/* AMD NTB Link Status Offset */
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AMD_LINK_STATUS_OFFSET = 0x68,
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/* AMD NTB register offset */
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AMD_CNTL_OFFSET = 0x200,
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/* NTB control register bits */
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PMM_REG_CTL = BIT(21),
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SMM_REG_CTL = BIT(20),
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SMM_REG_ACC_PATH = BIT(18),
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PMM_REG_ACC_PATH = BIT(17),
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NTB_CLK_EN = BIT(16),
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AMD_STA_OFFSET = 0x204,
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AMD_PGSLV_OFFSET = 0x208,
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AMD_SPAD_MUX_OFFSET = 0x20C,
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AMD_SPAD_OFFSET = 0x210,
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AMD_RSMU_HCID = 0x250,
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AMD_RSMU_SIID = 0x254,
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AMD_PSION_OFFSET = 0x300,
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AMD_SSION_OFFSET = 0x330,
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AMD_MMINDEX_OFFSET = 0x400,
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AMD_MMDATA_OFFSET = 0x404,
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AMD_SIDEINFO_OFFSET = 0x408,
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AMD_SIDE_MASK = BIT(0),
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AMD_SIDE_READY = BIT(1),
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/* limit register */
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AMD_ROMBARLMT_OFFSET = 0x410,
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AMD_BAR1LMT_OFFSET = 0x414,
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AMD_BAR23LMT_OFFSET = 0x418,
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AMD_BAR45LMT_OFFSET = 0x420,
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/* xlat address */
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AMD_ROMBARXLAT_OFFSET = 0x428,
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AMD_BAR1XLAT_OFFSET = 0x430,
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AMD_BAR23XLAT_OFFSET = 0x438,
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AMD_BAR45XLAT_OFFSET = 0x440,
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/* doorbell and interrupt */
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AMD_DBFM_OFFSET = 0x450,
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AMD_DBREQ_OFFSET = 0x454,
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AMD_MIRRDBSTAT_OFFSET = 0x458,
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AMD_DBMASK_OFFSET = 0x45C,
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AMD_DBSTAT_OFFSET = 0x460,
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AMD_INTMASK_OFFSET = 0x470,
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AMD_INTSTAT_OFFSET = 0x474,
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/* event type */
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AMD_PEER_FLUSH_EVENT = BIT(0),
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AMD_PEER_RESET_EVENT = BIT(1),
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AMD_PEER_D3_EVENT = BIT(2),
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AMD_PEER_PMETO_EVENT = BIT(3),
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AMD_PEER_D0_EVENT = BIT(4),
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AMD_LINK_UP_EVENT = BIT(5),
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AMD_LINK_DOWN_EVENT = BIT(6),
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AMD_EVENT_INTMASK = (AMD_PEER_FLUSH_EVENT |
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AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT |
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AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT |
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AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT),
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AMD_PMESTAT_OFFSET = 0x480,
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AMD_PMSGTRIG_OFFSET = 0x490,
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AMD_LTRLATENCY_OFFSET = 0x494,
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AMD_FLUSHTRIG_OFFSET = 0x498,
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/* SMU register*/
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AMD_SMUACK_OFFSET = 0x4A0,
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AMD_SINRST_OFFSET = 0x4A4,
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AMD_RSPNUM_OFFSET = 0x4A8,
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AMD_SMU_SPADMUTEX = 0x4B0,
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AMD_SMU_SPADOFFSET = 0x4B4,
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AMD_PEER_OFFSET = 0x400,
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};
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struct amd_ntb_softc {
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/* ntb.c context. Do not move! Must go first! */
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void *ntb_store;
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device_t device;
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enum amd_ntb_conn_type conn_type;
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struct amd_ntb_pci_bar_info bar_info[NTB_MAX_BARS];
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struct amd_ntb_int_info int_info[16];
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struct amd_ntb_vec *msix_vec;
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uint16_t allocated_interrupts;
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struct callout hb_timer;
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struct amd_ntb_hw_info *hw_info;
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uint8_t spad_count;
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uint8_t msix_vec_count;
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struct mtx db_mask_lock;
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volatile uint32_t ntb_ctl;
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volatile uint32_t lnk_sta;
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volatile uint32_t peer_sta;
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volatile uint32_t cntl_sta;
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uint16_t db_valid_mask;
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uint16_t db_mask;
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uint32_t int_mask;
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unsigned int self_spad;
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unsigned int peer_spad;
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};
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static void amd_init_side_info(struct amd_ntb_softc *ntb);
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static void amd_deinit_side_info(struct amd_ntb_softc *ntb);
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static int amd_ntb_detach(device_t device);
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#endif
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