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2d49248921
Unlike MSI-X, when a device uses multiple MSI interrupts, the entire group of interrupts are enabled/disabled at once in the relevant PCI config register. Currently, the interrupt code enables the IDT vector for each MSI interrupt when a handler is first registered. If the PCI device triggers an MSI interrupt which doesn't yet have a handler, this can trigger a panic when the Xrsvd ISR executes rather than treating it as a stray device interrupt. To fix, enable all the IDT vectors for an MSI group when the first interrupt handler is configured, and don't disable the IDT vectors until the last interrupt handler for the group is torn down. When migrating an MSI group between CPUs, enable/disable the entire group of IDT vectors if at least one interrupt handler is configured for the group. Reported by: jhay Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D42232 |
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| .. | ||
| acpica | ||
| bios | ||
| conf | ||
| cpufreq | ||
| include | ||
| iommu | ||
| isa | ||
| linux | ||
| pci | ||
| x86 | ||
| xen | ||