mirror of
https://github.com/freebsd/freebsd-src
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83 lines
2.4 KiB
ArmAsm
83 lines
2.4 KiB
ArmAsm
/*-
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* Copyright (c) 2016-2020 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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ENTRY(generic_bs_r_1)
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add a3, a1, a2
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lbu a0, 0(a3)
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ret
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END(generic_bs_r_1)
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ENTRY(generic_bs_r_2)
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add a3, a1, a2
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lhu a0, 0(a3)
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ret
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END(generic_bs_r_2)
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ENTRY(generic_bs_r_4)
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add a3, a1, a2
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lw a0, 0(a3)
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ret
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END(generic_bs_r_4)
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ENTRY(generic_bs_r_8)
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add a3, a1, a2
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ld a0, 0(a3)
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ret
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END(generic_bs_r_8)
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ENTRY(generic_bs_w_1)
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add a4, a1, a2
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sb a3, 0(a4)
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ret
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END(generic_bs_w_1)
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ENTRY(generic_bs_w_2)
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add a4, a1, a2
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sh a3, 0(a4)
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ret
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END(generic_bs_w_2)
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ENTRY(generic_bs_w_4)
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add a4, a1, a2
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sw a3, 0(a4)
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ret
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END(generic_bs_w_4)
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ENTRY(generic_bs_w_8)
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add a4, a1, a2
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sd a3, 0(a4)
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ret
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END(generic_bs_w_8)
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