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https://github.com/freebsd/freebsd-src
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787 lines
22 KiB
C
787 lines
22 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright (c) 2021, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file iavf_txrx_iflib.c
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* @brief Tx/Rx hotpath implementation for the iflib driver
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*
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* Contains functions used to implement the Tx and Rx hotpaths of the iflib
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* driver implementation.
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*/
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#include "iavf_iflib.h"
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#include "iavf_txrx_common.h"
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#ifdef RSS
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#include <net/rss_config.h>
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#endif
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/* Local Prototypes */
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static void iavf_rx_checksum(if_rxd_info_t ri, u32 status, u32 error, u8 ptype);
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static int iavf_isc_txd_encap(void *arg, if_pkt_info_t pi);
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static void iavf_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx);
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static int iavf_isc_txd_credits_update_hwb(void *arg, uint16_t txqid, bool clear);
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static int iavf_isc_txd_credits_update_dwb(void *arg, uint16_t txqid, bool clear);
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static void iavf_isc_rxd_refill(void *arg, if_rxd_update_t iru);
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static void iavf_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused,
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qidx_t pidx);
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static int iavf_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx,
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qidx_t budget);
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static int iavf_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri);
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/**
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* @var iavf_txrx_hwb
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* @brief iflib Tx/Rx operations for head write back
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*
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* iflib ops structure for when operating the device in head write back mode.
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*/
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struct if_txrx iavf_txrx_hwb = {
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iavf_isc_txd_encap,
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iavf_isc_txd_flush,
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iavf_isc_txd_credits_update_hwb,
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iavf_isc_rxd_available,
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iavf_isc_rxd_pkt_get,
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iavf_isc_rxd_refill,
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iavf_isc_rxd_flush,
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NULL
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};
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/**
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* @var iavf_txrx_dwb
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* @brief iflib Tx/Rx operations for descriptor write back
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*
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* iflib ops structure for when operating the device in descriptor write back
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* mode.
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*/
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struct if_txrx iavf_txrx_dwb = {
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iavf_isc_txd_encap,
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iavf_isc_txd_flush,
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iavf_isc_txd_credits_update_dwb,
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iavf_isc_rxd_available,
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iavf_isc_rxd_pkt_get,
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iavf_isc_rxd_refill,
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iavf_isc_rxd_flush,
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NULL
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};
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/**
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* iavf_is_tx_desc_done - Check if a Tx descriptor is ready
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* @txr: the Tx ring to check in
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* @idx: ring index to check
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*
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* @returns true if the descriptor has been written back by hardware, and
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* false otherwise.
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*/
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static bool
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iavf_is_tx_desc_done(struct tx_ring *txr, int idx)
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{
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return (((txr->tx_base[idx].cmd_type_offset_bsz >> IAVF_TXD_QW1_DTYPE_SHIFT)
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& IAVF_TXD_QW1_DTYPE_MASK) == IAVF_TX_DESC_DTYPE_DESC_DONE);
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}
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/**
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* iavf_tso_detect_sparse - detect TSO packets with too many segments
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* @segs: packet segments array
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* @nsegs: number of packet segments
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* @pi: packet information
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*
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* Hardware only transmits packets with a maximum of 8 descriptors. For TSO
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* packets, hardware needs to be able to build the split packets using 8 or
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* fewer descriptors. Additionally, the header must be contained within at
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* most 3 descriptors.
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*
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* To verify this, we walk the headers to find out how many descriptors the
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* headers require (usually 1). Then we ensure that, for each TSO segment, its
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* data plus the headers are contained within 8 or fewer descriptors.
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*
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* @returns zero if the packet is valid, one otherwise.
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*/
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static int
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iavf_tso_detect_sparse(bus_dma_segment_t *segs, int nsegs, if_pkt_info_t pi)
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{
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int count, curseg, i, hlen, segsz, seglen, tsolen;
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if (nsegs <= IAVF_MAX_TX_SEGS-2)
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return (0);
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segsz = pi->ipi_tso_segsz;
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curseg = count = 0;
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hlen = pi->ipi_ehdrlen + pi->ipi_ip_hlen + pi->ipi_tcp_hlen;
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tsolen = pi->ipi_len - hlen;
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i = 0;
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curseg = segs[0].ds_len;
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while (hlen > 0) {
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count++;
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if (count > IAVF_MAX_TX_SEGS - 2)
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return (1);
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if (curseg == 0) {
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i++;
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if (__predict_false(i == nsegs))
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return (1);
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curseg = segs[i].ds_len;
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}
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seglen = min(curseg, hlen);
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curseg -= seglen;
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hlen -= seglen;
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}
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while (tsolen > 0) {
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segsz = pi->ipi_tso_segsz;
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while (segsz > 0 && tsolen != 0) {
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count++;
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if (count > IAVF_MAX_TX_SEGS - 2) {
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return (1);
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}
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if (curseg == 0) {
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i++;
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if (__predict_false(i == nsegs)) {
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return (1);
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}
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curseg = segs[i].ds_len;
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}
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seglen = min(curseg, segsz);
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segsz -= seglen;
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curseg -= seglen;
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tsolen -= seglen;
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}
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count = 0;
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}
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return (0);
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}
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/**
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* iavf_tx_setup_offload - Setup Tx offload parameters
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* @que: pointer to the Tx queue
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* @pi: Tx packet info
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* @cmd: pointer to command descriptor value
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* @off: pointer to offset descriptor value
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*
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* Based on packet type and Tx offloads requested, sets up the command and
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* offset values for a Tx descriptor to enable the requested offloads.
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*/
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static void
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iavf_tx_setup_offload(struct iavf_tx_queue *que __unused,
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if_pkt_info_t pi, u32 *cmd, u32 *off)
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{
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switch (pi->ipi_etype) {
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#ifdef INET
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case ETHERTYPE_IP:
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if (pi->ipi_csum_flags & IAVF_CSUM_IPV4)
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*cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
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else
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*cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
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break;
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#endif
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#ifdef INET6
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case ETHERTYPE_IPV6:
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*cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
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break;
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#endif
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default:
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break;
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}
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*off |= (pi->ipi_ehdrlen >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
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*off |= (pi->ipi_ip_hlen >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
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switch (pi->ipi_ipproto) {
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case IPPROTO_TCP:
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if (pi->ipi_csum_flags & IAVF_CSUM_TCP) {
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*cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
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*off |= (pi->ipi_tcp_hlen >> 2) <<
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IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
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/* Check for NO_HEAD MDD event */
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MPASS(pi->ipi_tcp_hlen != 0);
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}
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break;
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case IPPROTO_UDP:
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if (pi->ipi_csum_flags & IAVF_CSUM_UDP) {
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*cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
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*off |= (sizeof(struct udphdr) >> 2) <<
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IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
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}
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break;
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case IPPROTO_SCTP:
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if (pi->ipi_csum_flags & IAVF_CSUM_SCTP) {
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*cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
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*off |= (sizeof(struct sctphdr) >> 2) <<
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IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
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}
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/* Fall Thru */
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default:
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break;
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}
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}
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/**
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* iavf_tso_setup - Setup TSO context descriptor
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* @txr: the Tx ring to process
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* @pi: packet info structure
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*
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* Enable hardware segmentation offload (TSO) for a given packet by creating
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* a context descriptor with the necessary details for offloading.
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*
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* @returns the new ring index to use for the data descriptor.
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*/
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static int
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iavf_tso_setup(struct tx_ring *txr, if_pkt_info_t pi)
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{
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if_softc_ctx_t scctx;
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struct iavf_tx_context_desc *TXD;
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u32 cmd, mss, type, tsolen;
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int idx, total_hdr_len;
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u64 type_cmd_tso_mss;
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idx = pi->ipi_pidx;
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TXD = (struct iavf_tx_context_desc *) &txr->tx_base[idx];
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total_hdr_len = pi->ipi_ehdrlen + pi->ipi_ip_hlen + pi->ipi_tcp_hlen;
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tsolen = pi->ipi_len - total_hdr_len;
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scctx = txr->que->vsi->shared;
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type = IAVF_TX_DESC_DTYPE_CONTEXT;
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cmd = IAVF_TX_CTX_DESC_TSO;
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/*
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* TSO MSS must not be less than 64; this prevents a
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* BAD_LSO_MSS MDD event when the MSS is too small.
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*/
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if (pi->ipi_tso_segsz < IAVF_MIN_TSO_MSS) {
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txr->mss_too_small++;
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pi->ipi_tso_segsz = IAVF_MIN_TSO_MSS;
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}
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mss = pi->ipi_tso_segsz;
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/* Check for BAD_LS0_MSS MDD event (mss too large) */
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MPASS(mss <= IAVF_MAX_TSO_MSS);
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/* Check for NO_HEAD MDD event (header lengths are 0) */
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MPASS(pi->ipi_ehdrlen != 0);
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MPASS(pi->ipi_ip_hlen != 0);
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/* Partial check for BAD_LSO_LEN MDD event */
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MPASS(tsolen != 0);
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/* Partial check for WRONG_SIZE MDD event (during TSO) */
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MPASS(total_hdr_len + mss <= IAVF_MAX_FRAME);
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type_cmd_tso_mss = ((u64)type << IAVF_TXD_CTX_QW1_DTYPE_SHIFT) |
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((u64)cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
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((u64)tsolen << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
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((u64)mss << IAVF_TXD_CTX_QW1_MSS_SHIFT);
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TXD->type_cmd_tso_mss = htole64(type_cmd_tso_mss);
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TXD->tunneling_params = htole32(0);
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txr->que->tso++;
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return ((idx + 1) & (scctx->isc_ntxd[0]-1));
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}
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#define IAVF_TXD_CMD (IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_RS)
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/**
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* iavf_isc_txd_encap - Encapsulate a Tx packet into descriptors
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* @arg: void pointer to the VSI structure
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* @pi: packet info to encapsulate
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*
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* This routine maps the mbufs to tx descriptors, allowing the
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* TX engine to transmit the packets.
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*
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* @returns 0 on success, positive on failure
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*/
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static int
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iavf_isc_txd_encap(void *arg, if_pkt_info_t pi)
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{
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struct iavf_vsi *vsi = arg;
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if_softc_ctx_t scctx = vsi->shared;
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struct iavf_tx_queue *que = &vsi->tx_queues[pi->ipi_qsidx];
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struct tx_ring *txr = &que->txr;
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int nsegs = pi->ipi_nsegs;
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bus_dma_segment_t *segs = pi->ipi_segs;
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struct iavf_tx_desc *txd = NULL;
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int i, j, mask, pidx_last;
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u32 cmd, off, tx_intr;
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if (__predict_false(pi->ipi_len < IAVF_MIN_FRAME)) {
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que->pkt_too_small++;
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return (EINVAL);
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}
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cmd = off = 0;
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i = pi->ipi_pidx;
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tx_intr = (pi->ipi_flags & IPI_TX_INTR);
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/* Set up the TSO/CSUM offload */
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if (pi->ipi_csum_flags & CSUM_OFFLOAD) {
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/* Set up the TSO context descriptor if required */
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if (pi->ipi_csum_flags & CSUM_TSO) {
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/* Prevent MAX_BUFF MDD event (for TSO) */
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if (iavf_tso_detect_sparse(segs, nsegs, pi))
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return (EFBIG);
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i = iavf_tso_setup(txr, pi);
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}
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iavf_tx_setup_offload(que, pi, &cmd, &off);
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}
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if (pi->ipi_mflags & M_VLANTAG)
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cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
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cmd |= IAVF_TX_DESC_CMD_ICRC;
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mask = scctx->isc_ntxd[0] - 1;
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/* Check for WRONG_SIZE MDD event */
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MPASS(pi->ipi_len >= IAVF_MIN_FRAME);
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#ifdef INVARIANTS
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if (!(pi->ipi_csum_flags & CSUM_TSO))
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MPASS(pi->ipi_len <= IAVF_MAX_FRAME);
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#endif
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for (j = 0; j < nsegs; j++) {
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bus_size_t seglen;
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txd = &txr->tx_base[i];
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seglen = segs[j].ds_len;
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/* Check for ZERO_BSIZE MDD event */
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MPASS(seglen != 0);
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txd->buffer_addr = htole64(segs[j].ds_addr);
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txd->cmd_type_offset_bsz =
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htole64(IAVF_TX_DESC_DTYPE_DATA
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| ((u64)cmd << IAVF_TXD_QW1_CMD_SHIFT)
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| ((u64)off << IAVF_TXD_QW1_OFFSET_SHIFT)
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| ((u64)seglen << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
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| ((u64)htole16(pi->ipi_vtag) << IAVF_TXD_QW1_L2TAG1_SHIFT));
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txr->tx_bytes += seglen;
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pidx_last = i;
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i = (i+1) & mask;
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}
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/* Set the last descriptor for report */
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txd->cmd_type_offset_bsz |=
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htole64(((u64)IAVF_TXD_CMD << IAVF_TXD_QW1_CMD_SHIFT));
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/* Add to report status array (if using TX interrupts) */
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if (!vsi->enable_head_writeback && tx_intr) {
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txr->tx_rsq[txr->tx_rs_pidx] = pidx_last;
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txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & mask;
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MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx);
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}
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pi->ipi_new_pidx = i;
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++txr->tx_packets;
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return (0);
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}
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/**
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* iavf_isc_txd_flush - Flush Tx ring
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* @arg: void pointer to the VSI
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* @txqid: the Tx queue to flush
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* @pidx: the ring index to flush to
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*
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* Advance the Transmit Descriptor Tail (Tdt), this tells the
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* hardware that this frame is available to transmit.
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*/
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static void
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iavf_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
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{
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struct iavf_vsi *vsi = arg;
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struct tx_ring *txr = &vsi->tx_queues[txqid].txr;
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/* Check for ENDLESS_TX MDD event */
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MPASS(pidx < vsi->shared->isc_ntxd[0]);
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wr32(vsi->hw, txr->tail, pidx);
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}
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/**
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* iavf_init_tx_ring - Initialize queue Tx ring
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* @vsi: pointer to the VSI
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* @que: pointer to queue to initialize
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*
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* (Re)Initialize a queue transmit ring by clearing its memory.
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*/
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void
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iavf_init_tx_ring(struct iavf_vsi *vsi, struct iavf_tx_queue *que)
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{
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struct tx_ring *txr = &que->txr;
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/* Clear the old ring contents */
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bzero((void *)txr->tx_base,
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(sizeof(struct iavf_tx_desc)) *
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(vsi->shared->isc_ntxd[0] + (vsi->enable_head_writeback ? 1 : 0)));
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wr32(vsi->hw, txr->tail, 0);
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}
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/**
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* iavf_get_tx_head - Get the index of the head of a ring
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* @que: queue to read
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*
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* Retrieve the value from the location the HW records its HEAD index
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*
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* @returns the index of the HW head of the Tx queue
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*/
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static inline u32
|
|
iavf_get_tx_head(struct iavf_tx_queue *que)
|
|
{
|
|
if_softc_ctx_t scctx = que->vsi->shared;
|
|
struct tx_ring *txr = &que->txr;
|
|
void *head = &txr->tx_base[scctx->isc_ntxd[0]];
|
|
|
|
return LE32_TO_CPU(*(volatile __le32 *)head);
|
|
}
|
|
|
|
/**
|
|
* iavf_isc_txd_credits_update_hwb - Update Tx ring credits
|
|
* @arg: void pointer to the VSI
|
|
* @qid: the queue id to update
|
|
* @clear: whether to update or only report current status
|
|
*
|
|
* Checks the number of packets in the queue that could be cleaned up.
|
|
*
|
|
* if clear is true, the iflib stack has cleaned the packets and is
|
|
* notifying the driver to update its processed ring pointer.
|
|
*
|
|
* @returns the number of packets in the ring that can be cleaned.
|
|
*
|
|
* @remark this function is intended for the head write back mode.
|
|
*/
|
|
static int
|
|
iavf_isc_txd_credits_update_hwb(void *arg, uint16_t qid, bool clear)
|
|
{
|
|
struct iavf_vsi *vsi = arg;
|
|
if_softc_ctx_t scctx = vsi->shared;
|
|
struct iavf_tx_queue *que = &vsi->tx_queues[qid];
|
|
struct tx_ring *txr = &que->txr;
|
|
int head, credits;
|
|
|
|
/* Get the Head WB value */
|
|
head = iavf_get_tx_head(que);
|
|
|
|
credits = head - txr->tx_cidx_processed;
|
|
if (credits < 0)
|
|
credits += scctx->isc_ntxd[0];
|
|
if (clear)
|
|
txr->tx_cidx_processed = head;
|
|
|
|
return (credits);
|
|
}
|
|
|
|
/**
|
|
* iavf_isc_txd_credits_update_dwb - Update Tx ring credits
|
|
* @arg: void pointer to the VSI
|
|
* @txqid: the queue id to update
|
|
* @clear: whether to update or only report current status
|
|
*
|
|
* Checks the number of packets in the queue that could be cleaned up.
|
|
*
|
|
* if clear is true, the iflib stack has cleaned the packets and is
|
|
* notifying the driver to update its processed ring pointer.
|
|
*
|
|
* @returns the number of packets in the ring that can be cleaned.
|
|
*
|
|
* @remark this function is intended for the descriptor write back mode.
|
|
*/
|
|
static int
|
|
iavf_isc_txd_credits_update_dwb(void *arg, uint16_t txqid, bool clear)
|
|
{
|
|
struct iavf_vsi *vsi = arg;
|
|
struct iavf_tx_queue *tx_que = &vsi->tx_queues[txqid];
|
|
if_softc_ctx_t scctx = vsi->shared;
|
|
struct tx_ring *txr = &tx_que->txr;
|
|
|
|
qidx_t processed = 0;
|
|
qidx_t cur, prev, ntxd, rs_cidx;
|
|
int32_t delta;
|
|
bool is_done;
|
|
|
|
rs_cidx = txr->tx_rs_cidx;
|
|
if (rs_cidx == txr->tx_rs_pidx)
|
|
return (0);
|
|
cur = txr->tx_rsq[rs_cidx];
|
|
MPASS(cur != QIDX_INVALID);
|
|
is_done = iavf_is_tx_desc_done(txr, cur);
|
|
|
|
if (!is_done)
|
|
return (0);
|
|
|
|
/* If clear is false just let caller know that there
|
|
* are descriptors to reclaim */
|
|
if (!clear)
|
|
return (1);
|
|
|
|
prev = txr->tx_cidx_processed;
|
|
ntxd = scctx->isc_ntxd[0];
|
|
do {
|
|
MPASS(prev != cur);
|
|
delta = (int32_t)cur - (int32_t)prev;
|
|
if (delta < 0)
|
|
delta += ntxd;
|
|
MPASS(delta > 0);
|
|
processed += delta;
|
|
prev = cur;
|
|
rs_cidx = (rs_cidx + 1) & (ntxd-1);
|
|
if (rs_cidx == txr->tx_rs_pidx)
|
|
break;
|
|
cur = txr->tx_rsq[rs_cidx];
|
|
MPASS(cur != QIDX_INVALID);
|
|
is_done = iavf_is_tx_desc_done(txr, cur);
|
|
} while (is_done);
|
|
|
|
txr->tx_rs_cidx = rs_cidx;
|
|
txr->tx_cidx_processed = prev;
|
|
|
|
return (processed);
|
|
}
|
|
|
|
/**
|
|
* iavf_isc_rxd_refill - Prepare descriptors for re-use
|
|
* @arg: void pointer to the VSI
|
|
* @iru: the Rx descriptor update structure
|
|
*
|
|
* Update Rx descriptors for a given queue so that they can be re-used by
|
|
* hardware for future packets.
|
|
*/
|
|
static void
|
|
iavf_isc_rxd_refill(void *arg, if_rxd_update_t iru)
|
|
{
|
|
struct iavf_vsi *vsi = arg;
|
|
if_softc_ctx_t scctx = vsi->shared;
|
|
struct rx_ring *rxr = &((vsi->rx_queues[iru->iru_qsidx]).rxr);
|
|
uint64_t *paddrs;
|
|
uint16_t next_pidx, pidx;
|
|
uint16_t count;
|
|
int i;
|
|
|
|
paddrs = iru->iru_paddrs;
|
|
pidx = iru->iru_pidx;
|
|
count = iru->iru_count;
|
|
|
|
for (i = 0, next_pidx = pidx; i < count; i++) {
|
|
rxr->rx_base[next_pidx].read.pkt_addr = htole64(paddrs[i]);
|
|
if (++next_pidx == scctx->isc_nrxd[0])
|
|
next_pidx = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* iavf_isc_rxd_flush - Notify hardware of new Rx descriptors
|
|
* @arg: void pointer to the VSI
|
|
* @rxqid: Rx queue to update
|
|
* @flid: unused parameter
|
|
* @pidx: ring index to update to
|
|
*
|
|
* Updates the tail pointer of the Rx ring, notifying hardware of new
|
|
* descriptors available for receiving packets.
|
|
*/
|
|
static void
|
|
iavf_isc_rxd_flush(void * arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx)
|
|
{
|
|
struct iavf_vsi *vsi = arg;
|
|
struct rx_ring *rxr = &vsi->rx_queues[rxqid].rxr;
|
|
|
|
wr32(vsi->hw, rxr->tail, pidx);
|
|
}
|
|
|
|
/**
|
|
* iavf_isc_rxd_available - Calculate number of available Rx descriptors
|
|
* @arg: void pointer to the VSI
|
|
* @rxqid: Rx queue to check
|
|
* @idx: starting index to check from
|
|
* @budget: maximum Rx budget
|
|
*
|
|
* Determines how many packets are ready to be processed in the Rx queue, up
|
|
* to the specified budget.
|
|
*
|
|
* @returns the number of packets ready to be processed, up to the budget.
|
|
*/
|
|
static int
|
|
iavf_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget)
|
|
{
|
|
struct iavf_vsi *vsi = arg;
|
|
struct rx_ring *rxr = &vsi->rx_queues[rxqid].rxr;
|
|
union iavf_rx_desc *rxd;
|
|
u64 qword;
|
|
uint32_t status;
|
|
int cnt, i, nrxd;
|
|
|
|
nrxd = vsi->shared->isc_nrxd[0];
|
|
|
|
for (cnt = 0, i = idx; cnt < nrxd - 1 && cnt <= budget;) {
|
|
rxd = &rxr->rx_base[i];
|
|
qword = le64toh(rxd->wb.qword1.status_error_len);
|
|
status = (qword & IAVF_RXD_QW1_STATUS_MASK)
|
|
>> IAVF_RXD_QW1_STATUS_SHIFT;
|
|
|
|
if ((status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) == 0)
|
|
break;
|
|
if (++i == nrxd)
|
|
i = 0;
|
|
if (status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))
|
|
cnt++;
|
|
}
|
|
|
|
return (cnt);
|
|
}
|
|
|
|
/**
|
|
* iavf_isc_rxd_pkt_get - Decapsulate packet from Rx descriptors
|
|
* @arg: void pointer to the VSI
|
|
* @ri: packet info structure
|
|
*
|
|
* Read packet data from the Rx ring descriptors and fill in the packet info
|
|
* structure so that the iflib stack can process the packet.
|
|
*
|
|
* @remark this routine executes in ithread context.
|
|
*
|
|
* @returns zero success, or EBADMSG if the packet is corrupted.
|
|
*/
|
|
static int
|
|
iavf_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
|
|
{
|
|
struct iavf_vsi *vsi = arg;
|
|
if_softc_ctx_t scctx = vsi->shared;
|
|
struct iavf_rx_queue *que = &vsi->rx_queues[ri->iri_qsidx];
|
|
struct rx_ring *rxr = &que->rxr;
|
|
union iavf_rx_desc *cur;
|
|
u32 status, error;
|
|
u16 plen;
|
|
u64 qword;
|
|
u8 ptype;
|
|
bool eop;
|
|
int i, cidx;
|
|
|
|
cidx = ri->iri_cidx;
|
|
i = 0;
|
|
do {
|
|
/* 5 descriptor receive limit */
|
|
MPASS(i < IAVF_MAX_RX_SEGS);
|
|
|
|
cur = &rxr->rx_base[cidx];
|
|
qword = le64toh(cur->wb.qword1.status_error_len);
|
|
status = (qword & IAVF_RXD_QW1_STATUS_MASK)
|
|
>> IAVF_RXD_QW1_STATUS_SHIFT;
|
|
error = (qword & IAVF_RXD_QW1_ERROR_MASK)
|
|
>> IAVF_RXD_QW1_ERROR_SHIFT;
|
|
plen = (qword & IAVF_RXD_QW1_LENGTH_PBUF_MASK)
|
|
>> IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
|
|
ptype = (qword & IAVF_RXD_QW1_PTYPE_MASK)
|
|
>> IAVF_RXD_QW1_PTYPE_SHIFT;
|
|
|
|
/* we should never be called without a valid descriptor */
|
|
MPASS((status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) != 0);
|
|
|
|
ri->iri_len += plen;
|
|
rxr->rx_bytes += plen;
|
|
|
|
cur->wb.qword1.status_error_len = 0;
|
|
eop = (status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT));
|
|
|
|
/*
|
|
** Make sure bad packets are discarded,
|
|
** note that only EOP descriptor has valid
|
|
** error results.
|
|
*/
|
|
if (eop && (error & (1 << IAVF_RX_DESC_ERROR_RXE_SHIFT))) {
|
|
rxr->desc_errs++;
|
|
return (EBADMSG);
|
|
}
|
|
ri->iri_frags[i].irf_flid = 0;
|
|
ri->iri_frags[i].irf_idx = cidx;
|
|
ri->iri_frags[i].irf_len = plen;
|
|
if (++cidx == vsi->shared->isc_nrxd[0])
|
|
cidx = 0;
|
|
i++;
|
|
} while (!eop);
|
|
|
|
/* capture data for dynamic ITR adjustment */
|
|
rxr->packets++;
|
|
rxr->rx_packets++;
|
|
|
|
if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0)
|
|
iavf_rx_checksum(ri, status, error, ptype);
|
|
ri->iri_flowid = le32toh(cur->wb.qword0.hi_dword.rss);
|
|
ri->iri_rsstype = iavf_ptype_to_hash(ptype);
|
|
if (status & (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
|
|
ri->iri_vtag = le16toh(cur->wb.qword0.lo_dword.l2tag1);
|
|
ri->iri_flags |= M_VLANTAG;
|
|
}
|
|
ri->iri_nfrags = i;
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* iavf_rx_checksum - Handle Rx hardware checksum indication
|
|
* @ri: Rx packet info structure
|
|
* @status: status from Rx descriptor
|
|
* @error: error from Rx descriptor
|
|
* @ptype: packet type
|
|
*
|
|
* Verify that the hardware indicated that the checksum is valid.
|
|
* Inform the stack about the status of checksum so that stack
|
|
* doesn't spend time verifying the checksum.
|
|
*/
|
|
static void
|
|
iavf_rx_checksum(if_rxd_info_t ri, u32 status, u32 error, u8 ptype)
|
|
{
|
|
struct iavf_rx_ptype_decoded decoded;
|
|
|
|
ri->iri_csum_flags = 0;
|
|
|
|
/* No L3 or L4 checksum was calculated */
|
|
if (!(status & (1 << IAVF_RX_DESC_STATUS_L3L4P_SHIFT)))
|
|
return;
|
|
|
|
decoded = decode_rx_desc_ptype(ptype);
|
|
|
|
/* IPv6 with extension headers likely have bad csum */
|
|
if (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP &&
|
|
decoded.outer_ip_ver == IAVF_RX_PTYPE_OUTER_IPV6) {
|
|
if (status &
|
|
(1 << IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT)) {
|
|
ri->iri_csum_flags = 0;
|
|
return;
|
|
}
|
|
}
|
|
|
|
ri->iri_csum_flags |= CSUM_L3_CALC;
|
|
|
|
/* IPv4 checksum error */
|
|
if (error & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT))
|
|
return;
|
|
|
|
ri->iri_csum_flags |= CSUM_L3_VALID;
|
|
ri->iri_csum_flags |= CSUM_L4_CALC;
|
|
|
|
/* L4 checksum error */
|
|
if (error & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT))
|
|
return;
|
|
|
|
ri->iri_csum_flags |= CSUM_L4_VALID;
|
|
ri->iri_csum_data |= htons(0xffff);
|
|
}
|