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713 lines
16 KiB
C
713 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/sx.h>
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#include <machine/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/gpio/gpiobusvar.h>
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#include "max77620.h"
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MALLOC_DEFINE(M_MAX77620_GPIO, "MAX77620 gpio", "MAX77620 GPIO");
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#define NGPIO 8
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#define GPIO_LOCK(_sc) sx_slock(&(_sc)->gpio_lock)
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#define GPIO_UNLOCK(_sc) sx_unlock(&(_sc)->gpio_lock)
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#define GPIO_ASSERT(_sc) sx_assert(&(_sc)->gpio_lock, SA_LOCKED)
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enum prop_id {
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CFG_BIAS_PULL_UP,
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CFG_BIAS_PULL_DOWN,
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CFG_OPEN_DRAIN,
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CFG_PUSH_PULL,
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CFG_ACTIVE_FPS_SRC,
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CFG_ACTIVE_PWRUP_SLOT,
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CFG_ACTIVE_PWRDOWN_SLOT,
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CFG_SUSPEND_FPS_SRC,
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CFG_SUSPEND_PWRUP_SLOT,
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CFG_SUSPEND_PWRDOWN_SLOT,
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PROP_ID_MAX_ID
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};
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static const struct {
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const char *name;
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enum prop_id id;
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} max77620_prop_names[] = {
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{"bias-pull-up", CFG_BIAS_PULL_UP},
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{"bias-pull-down", CFG_BIAS_PULL_DOWN},
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{"drive-open-drain", CFG_OPEN_DRAIN},
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{"drive-push-pull", CFG_PUSH_PULL},
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{"maxim,active-fps-source", CFG_ACTIVE_FPS_SRC},
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{"maxim,active-fps-power-up-slot", CFG_ACTIVE_PWRUP_SLOT},
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{"maxim,active-fps-power-down-slot", CFG_ACTIVE_PWRDOWN_SLOT},
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{"maxim,suspend-fps-source", CFG_SUSPEND_FPS_SRC},
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{"maxim,suspend-fps-power-up-slot", CFG_SUSPEND_PWRUP_SLOT},
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{"maxim,suspend-fps-power-down-slot", CFG_SUSPEND_PWRDOWN_SLOT},
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};
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/* Configuration for one pin group. */
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struct max77620_pincfg {
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bool alt_func;
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int params[PROP_ID_MAX_ID];
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};
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static char *altfnc_table[] = {
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"lpm-control-in",
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"fps-out",
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"32k-out1",
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"sd0-dvs-in",
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"sd1-dvs-in",
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"reference-out",
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};
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struct max77620_gpio_pin {
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int pin_caps;
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char pin_name[GPIOMAXNAME];
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uint8_t reg;
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/* Runtime data */
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bool alt_func; /* GPIO or alternate function */
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};
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/* --------------------------------------------------------------------------
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*
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* Pinmux functions.
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*/
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static int
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max77620_pinmux_get_function(struct max77620_softc *sc, char *name,
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struct max77620_pincfg *cfg)
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{
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int i;
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if (strcmp("gpio", name) == 0) {
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cfg->alt_func = false;
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return (0);
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}
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for (i = 0; i < nitems(altfnc_table); i++) {
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if (strcmp(altfnc_table[i], name) == 0) {
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cfg->alt_func = true;
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return (0);
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}
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}
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return (-1);
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}
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static int
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max77620_pinmux_set_fps(struct max77620_softc *sc, int pin_num,
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struct max77620_gpio_pin *pin)
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{
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#if 0
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struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
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int addr, ret;
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int param_val;
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int mask, shift;
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if ((pin < 1) || (pin > 3))
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return (0);
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switch (param) {
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case MAX77620_ACTIVE_FPS_SOURCE:
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case MAX77620_SUSPEND_FPS_SOURCE:
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mask = MAX77620_FPS_SRC_MASK;
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shift = MAX77620_FPS_SRC_SHIFT;
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param_val = fps_config->active_fps_src;
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if (param == MAX77620_SUSPEND_FPS_SOURCE)
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param_val = fps_config->suspend_fps_src;
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break;
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case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
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case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
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mask = MAX77620_FPS_PU_PERIOD_MASK;
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shift = MAX77620_FPS_PU_PERIOD_SHIFT;
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param_val = fps_config->active_power_up_slots;
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if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
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param_val = fps_config->suspend_power_up_slots;
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break;
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case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
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case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
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mask = MAX77620_FPS_PD_PERIOD_MASK;
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shift = MAX77620_FPS_PD_PERIOD_SHIFT;
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param_val = fps_config->active_power_down_slots;
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if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
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param_val = fps_config->suspend_power_down_slots;
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break;
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default:
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dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
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param, pin);
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return -EINVAL;
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}
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if (param_val < 0)
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return 0;
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ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
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if (ret < 0)
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dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
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return ret;
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#endif
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return (0);
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}
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static int
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max77620_pinmux_config_node(struct max77620_softc *sc, char *pin_name,
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struct max77620_pincfg *cfg)
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{
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struct max77620_gpio_pin *pin;
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uint8_t reg;
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int pin_num, rv;
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for (pin_num = 0; pin_num < sc->gpio_npins; pin_num++) {
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if (strcmp(sc->gpio_pins[pin_num]->pin_name, pin_name) == 0)
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break;
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}
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if (pin_num >= sc->gpio_npins) {
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device_printf(sc->dev, "Unknown pin: %s\n", pin_name);
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return (ENXIO);
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}
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pin = sc->gpio_pins[pin_num];
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rv = max77620_pinmux_set_fps(sc, pin_num, pin);
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if (rv != 0)
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return (rv);
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rv = RD1(sc, pin->reg, ®);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
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return (ENXIO);
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}
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if (cfg->alt_func) {
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pin->alt_func = true;
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sc->gpio_reg_ame |= 1 << pin_num;
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} else {
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pin->alt_func = false;
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sc->gpio_reg_ame &= ~(1 << pin_num);
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}
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/* Pull up/down. */
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switch (cfg->params[CFG_BIAS_PULL_UP]) {
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case 1:
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sc->gpio_reg_pue |= 1 << pin_num;
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break;
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case 0:
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sc->gpio_reg_pue &= ~(1 << pin_num);
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break;
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default:
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break;
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}
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switch (cfg->params[CFG_BIAS_PULL_DOWN]) {
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case 1:
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sc->gpio_reg_pde |= 1 << pin_num;
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break;
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case 0:
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sc->gpio_reg_pde &= ~(1 << pin_num);
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break;
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default:
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break;
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}
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/* Open drain/push-pull modes. */
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if (cfg->params[CFG_OPEN_DRAIN] == 1) {
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reg &= ~MAX77620_REG_GPIO_DRV(~0);
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reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);
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}
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if (cfg->params[CFG_PUSH_PULL] == 1) {
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reg &= ~MAX77620_REG_GPIO_DRV(~0);
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reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_PUSHPULL);
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}
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rv = WR1(sc, pin->reg, reg);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
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return (ENXIO);
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}
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return (0);
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}
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static int
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max77620_pinmux_read_node(struct max77620_softc *sc, phandle_t node,
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struct max77620_pincfg *cfg, char **pins, int *lpins)
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{
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char *function;
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int rv, i;
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*lpins = OF_getprop_alloc(node, "pins", (void **)pins);
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if (*lpins <= 0)
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return (ENOENT);
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/* Read function (mux) settings. */
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rv = OF_getprop_alloc(node, "function", (void **)&function);
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if (rv > 0) {
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rv = max77620_pinmux_get_function(sc, function, cfg);
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if (rv == -1) {
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device_printf(sc->dev,
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"Unknown function %s\n", function);
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OF_prop_free(function);
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return (ENXIO);
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}
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}
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/* Read numeric properties. */
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for (i = 0; i < PROP_ID_MAX_ID; i++) {
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rv = OF_getencprop(node, max77620_prop_names[i].name,
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&cfg->params[i], sizeof(cfg->params[i]));
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if (rv <= 0)
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cfg->params[i] = -1;
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}
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OF_prop_free(function);
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return (0);
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}
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static int
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max77620_pinmux_process_node(struct max77620_softc *sc, phandle_t node)
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{
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struct max77620_pincfg cfg;
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char *pins, *pname;
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int i, len, lpins, rv;
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rv = max77620_pinmux_read_node(sc, node, &cfg, &pins, &lpins);
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if (rv != 0)
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return (rv);
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len = 0;
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pname = pins;
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do {
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i = strlen(pname) + 1;
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rv = max77620_pinmux_config_node(sc, pname, &cfg);
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if (rv != 0) {
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device_printf(sc->dev,
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"Cannot configure pin: %s: %d\n", pname, rv);
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}
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len += i;
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pname += i;
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} while (len < lpins);
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if (pins != NULL)
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OF_prop_free(pins);
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return (rv);
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}
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int max77620_pinmux_configure(device_t dev, phandle_t cfgxref)
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{
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struct max77620_softc *sc;
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phandle_t node, cfgnode;
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uint8_t old_reg_pue, old_reg_pde, old_reg_ame;
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int rv;
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sc = device_get_softc(dev);
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cfgnode = OF_node_from_xref(cfgxref);
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old_reg_pue = sc->gpio_reg_pue;
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old_reg_pde = sc->gpio_reg_pde;
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old_reg_ame = sc->gpio_reg_ame;
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for (node = OF_child(cfgnode); node != 0; node = OF_peer(node)) {
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if (!ofw_bus_node_status_okay(node))
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continue;
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rv = max77620_pinmux_process_node(sc, node);
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if (rv != 0)
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device_printf(dev, "Failed to process pinmux");
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}
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if (old_reg_pue != sc->gpio_reg_pue) {
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rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue);
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if (rv != 0) {
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device_printf(sc->dev,
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"Cannot update PUE_GPIO register\n");
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return (ENXIO);
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}
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}
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if (old_reg_pde != sc->gpio_reg_pde) {
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rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde);
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if (rv != 0) {
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device_printf(sc->dev,
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"Cannot update PDE_GPIO register\n");
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return (ENXIO);
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}
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}
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if (old_reg_ame != sc->gpio_reg_ame) {
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rv = WR1(sc, MAX77620_REG_AME_GPIO, sc->gpio_reg_ame);
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if (rv != 0) {
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device_printf(sc->dev,
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"Cannot update PDE_GPIO register\n");
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return (ENXIO);
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}
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}
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return (0);
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}
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/* --------------------------------------------------------------------------
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*
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* GPIO
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*/
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device_t
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max77620_gpio_get_bus(device_t dev)
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{
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struct max77620_softc *sc;
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sc = device_get_softc(dev);
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return (sc->gpio_busdev);
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}
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int
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max77620_gpio_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = NGPIO - 1;
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return (0);
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}
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int
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max77620_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct max77620_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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*caps = sc->gpio_pins[pin]->pin_caps;
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GPIO_UNLOCK(sc);
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return (0);
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}
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int
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max77620_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct max77620_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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memcpy(name, sc->gpio_pins[pin]->pin_name, GPIOMAXNAME);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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max77620_gpio_get_mode(struct max77620_softc *sc, uint32_t pin_num,
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uint32_t *out_flags)
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{
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struct max77620_gpio_pin *pin;
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uint8_t reg;
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int rv;
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pin = sc->gpio_pins[pin_num];
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*out_flags = 0;
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rv = RD1(sc, pin->reg, ®);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
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return (ENXIO);
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}
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/* Pin function */
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pin->alt_func = sc->gpio_reg_ame & (1 << pin_num);
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/* Pull up/down. */
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if (sc->gpio_reg_pue & (1 << pin_num))
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*out_flags |= GPIO_PIN_PULLUP;
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if (sc->gpio_reg_pde & (1 << pin_num))
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*out_flags |= GPIO_PIN_PULLDOWN;
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/* Open drain/push-pull modes. */
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if (MAX77620_REG_GPIO_DRV_GET(reg) == MAX77620_REG_GPIO_DRV_PUSHPULL)
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*out_flags |= GPIO_PIN_PUSHPULL;
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else
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*out_flags |= GPIO_PIN_OPENDRAIN;
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/* Input/output modes. */
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if (MAX77620_REG_GPIO_DRV_GET(reg) == MAX77620_REG_GPIO_DRV_PUSHPULL)
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*out_flags |= GPIO_PIN_OUTPUT;
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else
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*out_flags |= GPIO_PIN_OUTPUT | GPIO_PIN_INPUT;
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return (0);
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}
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int
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max77620_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *out_flags)
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{
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struct max77620_softc *sc;
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int rv;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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#if 0 /* It colide with GPIO regulators */
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/* Is pin in GPIO mode ? */
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if (sc->gpio_pins[pin]->alt_func) {
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GPIO_UNLOCK(sc);
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return (ENXIO);
|
|
}
|
|
#endif
|
|
rv = max77620_gpio_get_mode(sc, pin, out_flags);
|
|
GPIO_UNLOCK(sc);
|
|
|
|
return (rv);
|
|
}
|
|
|
|
int
|
|
max77620_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
|
|
{
|
|
struct max77620_softc *sc;
|
|
struct max77620_gpio_pin *pin;
|
|
uint8_t reg;
|
|
uint8_t old_reg_pue, old_reg_pde;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (pin_num >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
pin = sc->gpio_pins[pin_num];
|
|
|
|
GPIO_LOCK(sc);
|
|
|
|
#if 0 /* It colide with GPIO regulators */
|
|
/* Is pin in GPIO mode ? */
|
|
if (pin->alt_func) {
|
|
GPIO_UNLOCK(sc);
|
|
return (ENXIO);
|
|
}
|
|
#endif
|
|
|
|
old_reg_pue = sc->gpio_reg_pue;
|
|
old_reg_pde = sc->gpio_reg_pde;
|
|
|
|
rv = RD1(sc, pin->reg, ®);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
|
|
GPIO_UNLOCK(sc);
|
|
return (ENXIO);
|
|
}
|
|
|
|
if (flags & GPIO_PIN_PULLUP)
|
|
sc->gpio_reg_pue |= 1 << pin_num;
|
|
else
|
|
sc->gpio_reg_pue &= ~(1 << pin_num);
|
|
|
|
if (flags & GPIO_PIN_PULLDOWN)
|
|
sc->gpio_reg_pde |= 1 << pin_num;
|
|
else
|
|
sc->gpio_reg_pde &= ~(1 << pin_num);
|
|
|
|
if (flags & GPIO_PIN_INPUT) {
|
|
reg &= ~MAX77620_REG_GPIO_DRV(~0);
|
|
reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);
|
|
reg &= ~MAX77620_REG_GPIO_OUTPUT_VAL(~0);
|
|
reg |= MAX77620_REG_GPIO_OUTPUT_VAL(1);
|
|
|
|
} else if (((flags & GPIO_PIN_OUTPUT) &&
|
|
(flags & GPIO_PIN_OPENDRAIN) == 0) ||
|
|
(flags & GPIO_PIN_PUSHPULL)) {
|
|
reg &= ~MAX77620_REG_GPIO_DRV(~0);
|
|
reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_PUSHPULL);
|
|
} else {
|
|
reg &= ~MAX77620_REG_GPIO_DRV(~0);
|
|
reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);
|
|
}
|
|
|
|
rv = WR1(sc, pin->reg, reg);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
|
|
return (ENXIO);
|
|
}
|
|
if (old_reg_pue != sc->gpio_reg_pue) {
|
|
rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev,
|
|
"Cannot update PUE_GPIO register\n");
|
|
GPIO_UNLOCK(sc);
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
if (old_reg_pde != sc->gpio_reg_pde) {
|
|
rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev,
|
|
"Cannot update PDE_GPIO register\n");
|
|
GPIO_UNLOCK(sc);
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
GPIO_UNLOCK(sc);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
max77620_gpio_pin_set(device_t dev, uint32_t pin, uint32_t val)
|
|
{
|
|
struct max77620_softc *sc;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),
|
|
MAX77620_REG_GPIO_OUTPUT_VAL(val));
|
|
GPIO_UNLOCK(sc);
|
|
return (rv);
|
|
}
|
|
|
|
int
|
|
max77620_gpio_pin_get(device_t dev, uint32_t pin, uint32_t *val)
|
|
{
|
|
struct max77620_softc *sc;
|
|
uint8_t tmp;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);
|
|
|
|
if (MAX77620_REG_GPIO_DRV_GET(tmp) == MAX77620_REG_GPIO_DRV_PUSHPULL)
|
|
*val = MAX77620_REG_GPIO_OUTPUT_VAL_GET(tmp);
|
|
else
|
|
*val = MAX77620_REG_GPIO_INPUT_VAL_GET(tmp);
|
|
GPIO_UNLOCK(sc);
|
|
if (rv != 0)
|
|
return (rv);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
max77620_gpio_pin_toggle(device_t dev, uint32_t pin)
|
|
{
|
|
struct max77620_softc *sc;
|
|
uint8_t tmp;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);
|
|
if (rv != 0) {
|
|
GPIO_UNLOCK(sc);
|
|
return (rv);
|
|
}
|
|
tmp ^= MAX77620_REG_GPIO_OUTPUT_VAL(~0);
|
|
rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),
|
|
tmp);
|
|
GPIO_UNLOCK(sc);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
max77620_gpio_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
|
|
int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags)
|
|
{
|
|
|
|
if (gcells != 2)
|
|
return (ERANGE);
|
|
*pin = gpios[0];
|
|
*flags= gpios[1];
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
max77620_gpio_attach(struct max77620_softc *sc, phandle_t node)
|
|
{
|
|
struct max77620_gpio_pin *pin;
|
|
int i, rv;
|
|
|
|
sx_init(&sc->gpio_lock, "MAX77620 GPIO lock");
|
|
|
|
sc->gpio_busdev = gpiobus_attach_bus(sc->dev);
|
|
if (sc->gpio_busdev == NULL)
|
|
return (ENXIO);
|
|
|
|
rv = RD1(sc, MAX77620_REG_PUE_GPIO, &sc->gpio_reg_pue);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot read PUE_GPIO register\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
rv = RD1(sc, MAX77620_REG_PDE_GPIO, &sc->gpio_reg_pde);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot read PDE_GPIO register\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
rv = RD1(sc, MAX77620_REG_AME_GPIO, &sc->gpio_reg_ame);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot read AME_GPIO register\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->gpio_npins = NGPIO;
|
|
sc->gpio_pins = malloc(sizeof(struct max77620_gpio_pin *) *
|
|
sc->gpio_npins, M_MAX77620_GPIO, M_WAITOK | M_ZERO);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
sc->gpio_pins[i] = malloc(sizeof(struct max77620_gpio_pin),
|
|
M_MAX77620_GPIO, M_WAITOK | M_ZERO);
|
|
pin = sc->gpio_pins[i];
|
|
sprintf(pin->pin_name, "gpio%d", i);
|
|
pin->pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
|
|
GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL |
|
|
GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN;
|
|
pin->reg = MAX77620_REG_GPIO0 + i;
|
|
}
|
|
|
|
return (0);
|
|
}
|