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Some x86 class CPUs have accelerated intrinsics for SHA1 and SHA256. Provide this functionality on CPUs that support it. This implements CRYPTO_SHA1, CRYPTO_SHA1_HMAC, and CRYPTO_SHA2_256_HMAC. Correctness: The cryptotest.py suite in tests/sys/opencrypto has been enhanced to verify SHA1 and SHA256 HMAC using standard NIST test vectors. The test passes on this driver. Additionally, jhb's cryptocheck tool has been used to compare various random inputs against OpenSSL. This test also passes. Rough performance averages on AMD Ryzen 1950X (4kB buffer): aesni: SHA1: ~8300 Mb/s SHA256: ~8000 Mb/s cryptosoft: ~1800 Mb/s SHA256: ~1800 Mb/s So ~4.4-4.6x speedup depending on algorithm choice. This is consistent with the results the Linux folks saw for 4kB buffers. The driver borrows SHA update code from sys/crypto sha1 and sha256. The intrinsic step function comes from Intel under a 3-clause BSDL.[0] The intel_sha_extensions_sha<foo>_intrinsic.c files were renamed and lightly modified (added const, resolved a warning or two; included the sha_sse header to declare the functions). [0]: https://software.intel.com/en-us/articles/intel-sha-extensions-implementations Reviewed by: jhb Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12452
112 lines
3.7 KiB
Groff
112 lines
3.7 KiB
Groff
.\" Copyright (c) 2010 Konstantin Belousov <kib@FreeBSD.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd September 26, 2017
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.Dt AESNI 4
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.Os
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.Sh NAME
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.Nm aesni
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.Nd "driver for the AES and SHA accelerator on x86 CPUs"
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device crypto"
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.Cd "device cryptodev"
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.Cd "device aesni"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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aesni_load="YES"
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.Ed
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.Sh DESCRIPTION
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Starting with Intel Westmere and AMD Bulldozer, some x86 processors implement a
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new set of instructions called AESNI.
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The set of six instructions accelerates the calculation of the key
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schedule for key lengths of 128, 192, and 256 of the Advanced
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Encryption Standard (AES) symmetric cipher, and provides a hardware
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implementation of the regular and the last encryption and decryption
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rounds.
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.Pp
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The processor capability is reported as AESNI in the Features2 line at boot.
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.Pp
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Starting with the Intel Goldmont and AMD Ryzen microarchitectures, some x86
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processors implement a new set of SHA instructions.
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The set of seven instructions accelerates the calculation of SHA1 and SHA256
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hashes.
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.Pp
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The processor capability is reported as SHA in the Structured Extended Features
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line at boot.
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.Pp
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The
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.Nm
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driver does not attach on systems that lack both CPU capabilities.
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On systems that support only one of AESNI or SHA extensions, the driver will
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attach and support that one function.
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.Pp
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The
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.Nm
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driver registers itself to accelerate AES and SHA operations for
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.Xr crypto 4 .
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Besides speed, the advantage of using the
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.Nm
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driver is that the AESNI operation
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is data-independent, thus eliminating some attack vectors based on
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measuring cache use and timings typically present in table-driven
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implementations.
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.Sh SEE ALSO
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.Xr crypt 3 ,
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.Xr crypto 4 ,
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.Xr intro 4 ,
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.Xr ipsec 4 ,
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.Xr padlock 4 ,
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.Xr random 4 ,
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.Xr crypto 9
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.Sh HISTORY
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The
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.Nm
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driver first appeared in
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.Fx 9.0 .
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SHA support was added in
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.Fx 12.0 .
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.Sh AUTHORS
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.An -nosplit
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The
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.Nm
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driver was written by
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.An Konstantin Belousov Aq Mt kib@FreeBSD.org
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and
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.An Conrad Meyer Aq Mt cem@FreeBSD.org .
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The key schedule calculation code was adopted from the sample provided
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by Intel and used in the analogous
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.Ox
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driver.
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The hash step intrinsics implementations were supplied by Intel.
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