Ruslan Bukin 1fdcc5e5c0 Start support for the RISC-V 64-bit architecture developed by UC Berkeley. ... RISC-V is a new ISA designed to support computer research and education, and is now become a standard open architecture for industry implementations. This is a minimal set of changes required to run 'make kernel-toolchain' using external (GNU) toolchain. The FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv. Reviewed by: andrew, bdrewery, emaste, imp Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4445		2015-12-11 22:55:23 +00:00
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aarch64	Add pthread_md.h for arm64.	2015-03-30 19:10:09 +00:00
amd64	Disable SSE in libthr	2015-08-05 12:53:55 +00:00
arm/include	Merge all the copies of _tcb_ctor and _tcb_dtor.	2015-01-21 16:41:05 +00:00
i386	Disable SSE in libthr	2015-08-05 12:53:55 +00:00
mips/include	Merge all the copies of _tcb_ctor and _tcb_dtor.	2015-01-21 16:41:05 +00:00
powerpc/include	Merge all the copies of _tcb_ctor and _tcb_dtor.	2015-01-21 16:41:05 +00:00
riscv	Start support for the RISC-V 64-bit architecture developed by UC Berkeley.	2015-12-11 22:55:23 +00:00
sparc64	Merge all the copies of _tcb_ctor and _tcb_dtor.	2015-01-21 16:41:05 +00:00