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acae33b029
Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors. |
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|---|---|---|
| .. | ||
| aicasm | ||
| ahc_eisa.c | ||
| ahc_pci.c | ||
| ahd_pci.c | ||
| aic7xxx.c | ||
| aic7xxx.h | ||
| aic7xxx.reg | ||
| aic7xxx.seq | ||
| aic7xxx_93cx6.c | ||
| aic7xxx_93cx6.h | ||
| aic7xxx_inline.h | ||
| aic7xxx_osm.c | ||
| aic7xxx_osm.h | ||
| aic7xxx_pci.c | ||
| aic79xx.c | ||
| aic79xx.h | ||
| aic79xx.reg | ||
| aic79xx.seq | ||
| aic79xx_inline.h | ||
| aic79xx_osm.c | ||
| aic79xx_osm.h | ||
| aic79xx_pci.c | ||
| aic7770.c | ||