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83 lines
4.1 KiB
C
83 lines
4.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DEV_XILINX_XLNX_PCIB_H_
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#define _DEV_XILINX_XLNX_PCIB_H_
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#define XLNX_PCIE_VSEC 0x12c
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#define XLNX_PCIE_BIR 0x130 /* Bridge Info Register */
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#define XLNX_PCIE_BSCR 0x134 /* Bridge Status and Control */
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#define XLNX_PCIE_IDR 0x138 /* Interrupt Decode Register */
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#define XLNX_PCIE_IMR 0x13C /* Interrupt Mask Register */
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#define IMR_LINK_DOWN (1 << 0)
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#define IMR_HOT_RESET (1 << 3)
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#define IMR_CFG_COMPL_STATUS_S 5
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#define IMR_CFG_COMPL_STATUS_M (0x7 << IMR_CFG_COMPL_STATUS_S)
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#define IMR_CFG_TIMEOUT (1 << 8)
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#define IMR_CORRECTABLE (1 << 9)
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#define IMR_NON_FATAL (1 << 10)
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#define IMR_FATAL (1 << 11)
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#define IMR_INTX (1 << 16) /* INTx Interrupt Received */
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#define IMR_MSI (1 << 17) /* MSI Interrupt Received */
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#define IMR_SLAVE_UNSUPP_REQ (1 << 20)
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#define IMR_SLAVE_UNEXP_COMPL (1 << 21)
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#define IMR_SLAVE_COMPL_TIMOUT (1 << 22)
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#define IMR_SLAVE_ERROR_POISON (1 << 23)
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#define IMR_SLAVE_COMPL_ABORT (1 << 24)
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#define IMR_SLAVE_ILLEG_BURST (1 << 25)
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#define IMR_MASTER_DECERR (1 << 26)
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#define IMR_MASTER_SLVERR (1 << 27)
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#define XLNX_PCIE_BLR 0x140 /* Bus Location Register */
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#define XLNX_PCIE_PHYSCR 0x144 /* PHY Status/Control Register */
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#define PHYSCR_LINK_UP (1 << 11) /* Current PHY Link-up state */
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#define XLNX_PCIE_RPSCR 0x148 /* Root Port Status/Control Register */
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#define RPSCR_BE (1 << 0) /* Bridge Enable */
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#define XLNX_PCIE_RPMSIBR1 0x14C /* Root Port MSI Base Register 1 */
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#define XLNX_PCIE_RPMSIBR2 0x150 /* Root Port MSI Base Register 2 */
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#define XLNX_PCIE_RPERRFRR 0x154 /* Root Port Error FIFO Read */
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#define RPERRFRR_VALID (1 << 18) /* Indicates whether read succeeded.*/
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#define RPERRFRR_REQ_ID_S 0 /* Requester of the error message. */
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#define RPERRFRR_REQ_ID_M (0xffff << RPERRFRR_REQ_ID_S)
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#define XLNX_PCIE_RPIFRR1 0x158 /* Root Port Interrupt FIFO Read 1 */
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#define XLNX_PCIE_RPIFRR2 0x15C /* Root Port Interrupt FIFO Read 2 */
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#define XLNX_PCIE_RPID2 0x160 /* Root Port Interrupt Decode 2 */
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#define XLNX_PCIE_RPID2_MASK 0x164 /* Root Port Interrupt Decode 2 Mask */
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#define XLNX_PCIE_RPMSIID1 0x170 /* Root Port MSI Interrupt Decode 1 */
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#define XLNX_PCIE_RPMSIID2 0x174 /* Root Port MSI Interrupt Decode 2 */
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#define XLNX_PCIE_RPMSIID1_MASK 0x178 /* Root Port MSI Int. Decode 1 Mask */
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#define XLNX_PCIE_RPMSIID2_MASK 0x17C /* Root Port MSI Int. Decode 2 Mask */
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#define XLNX_PCIE_CCR 0x168 /* Configuration Control Register */
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#define XLNX_PCIE_VSEC_CR 0x200 /* VSEC Capability Register 2 */
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#define XLNX_PCIE_VSEC_HR 0x204 /* VSEC Header Register 2 */
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#endif /* !_DEV_XILINX_XLNX_PCIB_H_ */
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