mirror of
https://github.com/freebsd/freebsd-src
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308 lines
9.3 KiB
C
308 lines
9.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IF_TSEC_H
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#define _IF_TSEC_H
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#include <dev/ofw/openfirm.h>
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#define TSEC_RX_NUM_DESC 256
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#define TSEC_TX_NUM_DESC 256
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#define TSEC_TX_MAX_DMA_SEGS 8
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/* Interrupt Coalescing types */
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#define TSEC_IC_RX 0
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#define TSEC_IC_TX 1
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/* eTSEC ID */
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#define TSEC_ETSEC_ID 0x0124
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/* Frame sizes */
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#define TSEC_MIN_FRAME_SIZE 64
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#define TSEC_MAX_FRAME_SIZE 9600
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struct tsec_bufmap {
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bus_dmamap_t map;
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int map_initialized;
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struct mbuf *mbuf;
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};
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struct tsec_softc {
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/* XXX MII bus requires that struct ifnet is first!!! */
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if_t tsec_ifp;
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struct mtx transmit_lock; /* transmitter lock */
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struct mtx receive_lock; /* receiver lock */
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phandle_t node;
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device_t dev;
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device_t tsec_miibus;
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struct mii_data *tsec_mii; /* MII media control */
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int tsec_link;
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bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */
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bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */
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bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */
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uint32_t tx_idx_head; /* TX head descriptor/bufmap index */
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uint32_t tx_idx_tail; /* TX tail descriptor/bufmap index */
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struct tsec_desc *tsec_tx_vaddr;/* virtual address of TX descriptors */
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struct tsec_bufmap tx_bufmap[TSEC_TX_NUM_DESC];
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bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */
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bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */
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bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */
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struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */
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struct rx_data_type {
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bus_dmamap_t map; /* mbuf map */
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struct mbuf *mbuf;
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uint32_t paddr; /* DMA address of buffer */
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} rx_data[TSEC_RX_NUM_DESC];
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uint32_t rx_cur_desc_cnt;
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struct resource *sc_rres; /* register resource */
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int sc_rrid; /* register rid */
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struct {
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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} sc_bas;
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struct resource *sc_transmit_ires;
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void *sc_transmit_ihand;
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int sc_transmit_irid;
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struct resource *sc_receive_ires;
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void *sc_receive_ihand;
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int sc_receive_irid;
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struct resource *sc_error_ires;
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void *sc_error_ihand;
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int sc_error_irid;
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int tsec_if_flags;
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int is_etsec;
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/* Watchdog and MII tick related */
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struct callout tsec_callout;
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int tsec_watchdog;
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/* interrupt coalescing */
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struct mtx ic_lock;
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uint32_t rx_ic_time; /* RW, valid values 0..65535 */
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uint32_t rx_ic_count; /* RW, valid values 0..255 */
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uint32_t tx_ic_time;
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uint32_t tx_ic_count;
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/* currently received frame */
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struct mbuf *frame;
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int phyaddr;
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bus_space_tag_t phy_bst;
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bus_space_handle_t phy_bsh;
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int phy_regoff;
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uint32_t tsec_rx_raddr; /* real address of RX descriptors */
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uint32_t tsec_tx_raddr; /* real address of TX descriptors */
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};
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/* interface to get/put generic objects */
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#define TSEC_CNT_INIT(cnt, wrap) ((cnt) = ((wrap) - 1))
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#define TSEC_INC(count, wrap) (count = ((count) + 1) & ((wrap) - 1))
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#define TSEC_GET_GENERIC(hand, tab, count, wrap) \
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((hand)->tab[TSEC_INC((hand)->count, wrap)])
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#define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \
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((hand)->tab[TSEC_INC((hand)->count, wrap)] = val)
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#define TSEC_BACK_GENERIC(sc, count, wrap) do { \
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if ((sc)->count > 0) \
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(sc)->count--; \
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else \
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(sc)->count = (wrap) - 1; \
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} while (0)
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#define TSEC_FREE_TX_DESC(sc) \
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(((sc)->tx_idx_tail - (sc)->tx_idx_head - 1) & (TSEC_TX_NUM_DESC - 1))
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/* interface for manage rx tsec_desc */
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#define TSEC_RX_DESC_CNT_INIT(sc) do { \
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TSEC_CNT_INIT((sc)->rx_cur_desc_cnt, TSEC_RX_NUM_DESC); \
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} while (0)
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#define TSEC_GET_CUR_RX_DESC(sc) \
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&TSEC_GET_GENERIC(sc, tsec_rx_vaddr, rx_cur_desc_cnt, \
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TSEC_RX_NUM_DESC)
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#define TSEC_BACK_CUR_RX_DESC(sc) \
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TSEC_BACK_GENERIC(sc, rx_cur_desc_cnt, TSEC_RX_NUM_DESC)
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#define TSEC_GET_CUR_RX_DESC_CNT(sc) \
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((sc)->rx_cur_desc_cnt)
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/* init all counters (for init only!) */
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#define TSEC_TX_RX_COUNTERS_INIT(sc) do { \
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sc->tx_idx_head = 0; \
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sc->tx_idx_tail = 0; \
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TSEC_RX_DESC_CNT_INIT(sc); \
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} while (0)
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/* read/write bus functions */
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#define TSEC_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg))
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#define TSEC_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val))
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extern struct mtx tsec_phy_mtx;
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#define TSEC_PHY_LOCK(sc) mtx_lock(&tsec_phy_mtx)
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#define TSEC_PHY_UNLOCK(sc) mtx_unlock(&tsec_phy_mtx)
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#define TSEC_PHY_READ(sc, reg) \
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bus_space_read_4((sc)->phy_bst, (sc)->phy_bsh, \
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(reg) + (sc)->phy_regoff)
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#define TSEC_PHY_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->phy_bst, (sc)->phy_bsh, \
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(reg) + (sc)->phy_regoff, (val))
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/* Lock for transmitter */
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#define TSEC_TRANSMIT_LOCK(sc) do { \
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mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->transmit_lock); \
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} while (0)
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#define TSEC_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock)
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#define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED)
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/* Lock for receiver */
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#define TSEC_RECEIVE_LOCK(sc) do { \
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mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->receive_lock); \
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} while (0)
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#define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock)
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#define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED)
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/* Lock for interrupts coalescing */
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#define TSEC_IC_LOCK(sc) do { \
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mtx_assert(&(sc)->ic_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->ic_lock); \
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} while (0)
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#define TSEC_IC_UNLOCK(sc) mtx_unlock(&(sc)->ic_lock)
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#define TSEC_IC_LOCK_ASSERT(sc) mtx_assert(&(sc)->ic_lock, MA_OWNED)
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/* Global tsec lock (with all locks) */
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#define TSEC_GLOBAL_LOCK(sc) do { \
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if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \
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(mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \
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panic("tsec deadlock possibility detection!"); \
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} \
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mtx_lock(&(sc)->transmit_lock); \
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mtx_lock(&(sc)->receive_lock); \
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} while (0)
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#define TSEC_GLOBAL_UNLOCK(sc) do { \
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TSEC_RECEIVE_UNLOCK(sc); \
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TSEC_TRANSMIT_UNLOCK(sc); \
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} while (0)
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#define TSEC_GLOBAL_LOCK_ASSERT(sc) do { \
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TSEC_TRANSMIT_LOCK_ASSERT(sc); \
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TSEC_RECEIVE_LOCK_ASSERT(sc); \
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} while (0)
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/* From global to {transmit,receive} */
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#define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \
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mtx_unlock(&(sc)->receive_lock);\
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} while (0)
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#define TSEC_GLOBAL_TO_RECEIVE_LOCK(sc) do { \
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mtx_unlock(&(sc)->transmit_lock);\
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} while (0)
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struct tsec_desc {
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volatile uint16_t flags; /* descriptor flags */
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volatile uint16_t length; /* buffer length */
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volatile uint32_t bufptr; /* buffer pointer */
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};
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#define TSEC_READ_RETRY 10000
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#define TSEC_READ_DELAY 100
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/* Structures and defines for TCP/IP Off-load */
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struct tsec_tx_fcb {
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volatile uint16_t flags;
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volatile uint8_t l4_offset;
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volatile uint8_t l3_offset;
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volatile uint16_t ph_chsum;
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volatile uint16_t vlan;
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};
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struct tsec_rx_fcb {
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volatile uint16_t flags;
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volatile uint8_t rq_index;
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volatile uint8_t protocol;
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volatile uint16_t unused;
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volatile uint16_t vlan;
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};
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#define TSEC_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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#define TSEC_TX_FCB_IP4 TSEC_TX_FCB_L3_IS_IP
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#define TSEC_TX_FCB_IP6 (TSEC_TX_FCB_L3_IS_IP | TSEC_TX_FCB_L3_IS_IP6)
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#define TSEC_TX_FCB_TCP TSEC_TX_FCB_L4_IS_TCP_UDP
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#define TSEC_TX_FCB_UDP (TSEC_TX_FCB_L4_IS_TCP_UDP | TSEC_TX_FCB_L4_IS_UDP)
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#define TSEC_RX_FCB_IP_CSUM_CHECKED(flags) \
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((flags & (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP6_FOUND | \
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TSEC_RX_FCB_IP_CSUM | TSEC_RX_FCB_PARSE_ERROR)) \
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== (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP_CSUM))
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#define TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) \
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((flags & (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM \
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| TSEC_RX_FCB_PARSE_ERROR)) \
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== (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM))
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/* Prototypes */
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int tsec_attach(struct tsec_softc *sc);
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int tsec_detach(struct tsec_softc *sc);
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void tsec_error_intr(void *arg);
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void tsec_receive_intr(void *arg);
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void tsec_transmit_intr(void *arg);
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int tsec_miibus_readreg(device_t dev, int phy, int reg);
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int tsec_miibus_writereg(device_t dev, int phy, int reg, int value);
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void tsec_miibus_statchg(device_t dev);
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int tsec_resume(device_t dev); /* XXX */
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int tsec_shutdown(device_t dev);
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int tsec_suspend(device_t dev); /* XXX */
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void tsec_get_hwaddr(struct tsec_softc *sc, uint8_t *addr);
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#endif /* _IF_TSEC_H */
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