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688 lines
19 KiB
C
688 lines
19 KiB
C
/* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Sundance Technology PCI vendor ID
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*/
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#define VENDOR_SUNDANCETI 0x13f0
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/*
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* Tamarack Microelectronics PCI vendor ID
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*/
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#define VENDOR_TAMARACK 0x143d
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/*
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* D-Link Systems PCI vendor ID
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*/
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#define VENDOR_DLINK 0x1186
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/*
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* Antares Microsystems PCI vendor ID
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*/
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#define VENDOR_ANTARES 0x1754
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/*
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* Sundance Technology device ID
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*/
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#define DEVICEID_SUNDANCETI_ST1023 0x1023
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#define DEVICEID_SUNDANCETI_ST2021 0x2021
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#define DEVICEID_TAMARACK_TC9021 0x1021
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#define DEVICEID_TAMARACK_TC9021_ALT 0x9021
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/*
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* D-Link Systems device ID
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*/
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#define DEVICEID_DLINK_DL4000 0x4000
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/*
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* Antares Microsystems device ID
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*/
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#define DEVICEID_ANTARES_TC9021 0x1021
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/*
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* Register description for the Sundance Tech. TC9021 10/100/1000
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* Ethernet controller.
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*
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* Note that while DMA addresses are all in 64-bit fields, only
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* the lower 40 bits of a DMA address are valid.
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*/
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#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
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#define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR
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#else
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#define STGE_DMA_MAXADDR 0xFFFFFFFFFF
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#endif
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/*
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* Register access macros
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*/
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#define CSR_WRITE_4(_sc, reg, val) \
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bus_write_4((_sc)->sc_res[0], (reg), (val))
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#define CSR_WRITE_2(_sc, reg, val) \
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bus_write_2((_sc)->sc_res[0], (reg), (val))
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#define CSR_WRITE_1(_sc, reg, val) \
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bus_write_1((_sc)->sc_res[0], (reg), (val))
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#define CSR_READ_4(_sc, reg) \
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bus_read_4((_sc)->sc_res[0], (reg))
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#define CSR_READ_2(_sc, reg) \
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bus_read_2((_sc)->sc_res[0], (reg))
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#define CSR_READ_1(_sc, reg) \
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bus_read_1((_sc)->sc_res[0], (reg))
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#define CSR_BARRIER(_sc, reg, length, flags) \
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bus_barrier((_sc)->sc_res[0], reg, length, flags)
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/*
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* TC9021 buffer fragment descriptor.
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*/
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struct stge_frag {
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uint64_t frag_word0; /* address, length */
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};
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#define FRAG_ADDR(x) (((uint64_t)(x)) << 0)
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#define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL)
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#define FRAG_LEN(x) (((uint64_t)(x)) << 48)
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#define FRAG_LEN_MASK FRAG_LEN(0xffffULL)
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/*
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* TC9021 Transmit Frame Descriptor. Note the number of fragments
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* here is arbitrary, but we can't have any more than 15.
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*/
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#define STGE_NTXFRAGS 15
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struct stge_tfd {
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uint64_t tfd_next; /* next TFD in list */
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uint64_t tfd_control; /* control bits */
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/* the buffer fragments */
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struct stge_frag tfd_frags[STGE_NTXFRAGS];
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};
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#define TFD_FrameId(x) ((x) << 0)
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#define TFD_FrameId_MAX 0xffff
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#define TFD_WordAlign(x) ((x) << 16)
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#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */
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#define TFD_WordAlign_word 2 /* align to word in TxFIFO */
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#define TFD_WordAlign_disable 1 /* disable alignment */
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#define TFD_TCPChecksumEnable (1ULL << 18)
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#define TFD_UDPChecksumEnable (1ULL << 19)
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#define TFD_IPChecksumEnable (1ULL << 20)
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#define TFD_FcsAppendDisable (1ULL << 21)
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#define TFD_TxIndicate (1ULL << 22)
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#define TFD_TxDMAIndicate (1ULL << 23)
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#define TFD_FragCount(x) ((x) << 24)
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#define TFD_VLANTagInsert (1ULL << 28)
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#define TFD_TFDDone (1ULL << 31)
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#define TFD_VID(x) (((uint64_t)(x)) << 32)
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#define TFD_CFI (1ULL << 44)
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#define TFD_UserPriority(x) (((uint64_t)(x)) << 45)
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/*
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* TC9021 Receive Frame Descriptor. Each RFD has a single fragment
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* in it, and the chip tells us the beginning and end of the frame.
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*/
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struct stge_rfd {
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uint64_t rfd_next; /* next RFD in list */
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uint64_t rfd_status; /* status bits */
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struct stge_frag rfd_frag; /* the buffer */
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};
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/* Low word of rfd_status */
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#define RFD_RxStatus(x) ((x) & 0xffffffff)
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#define RFD_RxDMAFrameLen(x) ((x) & 0xffff)
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#define RFD_RxFIFOOverrun 0x00010000
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#define RFD_RxRuntFrame 0x00020000
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#define RFD_RxAlignmentError 0x00040000
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#define RFD_RxFCSError 0x00080000
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#define RFD_RxOversizedFrame 0x00100000
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#define RFD_RxLengthError 0x00200000
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#define RFD_VLANDetected 0x00400000
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#define RFD_TCPDetected 0x00800000
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#define RFD_TCPError 0x01000000
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#define RFD_UDPDetected 0x02000000
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#define RFD_UDPError 0x04000000
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#define RFD_IPDetected 0x08000000
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#define RFD_IPError 0x10000000
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#define RFD_FrameStart 0x20000000
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#define RFD_FrameEnd 0x40000000
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#define RFD_RFDDone 0x80000000
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/* High word of rfd_status */
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#define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff)
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/*
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* EEPROM offsets.
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*/
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#define STGE_EEPROM_ConfigParam 0x00
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#define STGE_EEPROM_AsicCtrl 0x01
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#define STGE_EEPROM_SubSystemVendorId 0x02
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#define STGE_EEPROM_SubSystemId 0x03
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#define STGE_EEPROM_LEDMode 0x06
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#define STGE_EEPROM_StationAddress0 0x10
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#define STGE_EEPROM_StationAddress1 0x11
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#define STGE_EEPROM_StationAddress2 0x12
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/*
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* The TC9021 register space.
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*/
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#define STGE_DMACtrl 0x00
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#define DMAC_RxDMAComplete (1U << 3)
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#define DMAC_RxDMAPollNow (1U << 4)
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#define DMAC_TxDMAComplete (1U << 11)
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#define DMAC_TxDMAPollNow (1U << 12)
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#define DMAC_TxDMAInProg (1U << 15)
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#define DMAC_RxEarlyDisable (1U << 16)
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#define DMAC_MWIDisable (1U << 18)
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#define DMAC_TxWriteBackDisable (1U << 19)
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#define DMAC_TxBurstLimit(x) ((x) << 20)
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#define DMAC_TargetAbort (1U << 30)
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#define DMAC_MasterAbort (1U << 31)
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#define STGE_RxDMAStatus 0x08
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#define STGE_TFDListPtrLo 0x10
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#define STGE_TFDListPtrHi 0x14
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#define STGE_TxDMABurstThresh 0x18 /* 8-bit */
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#define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */
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#define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */
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#define STGE_RFDListPtrLo 0x1c
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#define STGE_RFDListPtrHi 0x20
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#define STGE_RxDMABurstThresh 0x24 /* 8-bit */
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#define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */
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#define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */
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#define STGE_RxDMAIntCtrl 0x28
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#define RDIC_RxFrameCount(x) ((x) & 0xff)
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#define RDIC_PriorityThresh(x) ((x) << 10)
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#define RDIC_RxDMAWaitTime(x) ((x) << 16)
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/*
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* Number of receive frames transferred via DMA before a Rx interrupt is issued.
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*/
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#define STGE_RXINT_NFRAME_DEFAULT 8
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#define STGE_RXINT_NFRAME_MIN 1
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#define STGE_RXINT_NFRAME_MAX 255
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/*
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* Maximum amount of time (in 64ns increments) to wait before issuing a Rx
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* interrupt if number of frames recevied is less than STGE_RXINT_NFRAME
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* (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX)
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*/
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#define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */
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#define STGE_RXINT_DMAWAIT_MIN 0
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#define STGE_RXINT_DMAWAIT_MAX 4194
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#define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64)
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#define STGE_DebugCtrl 0x2c /* 16-bit */
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#define DC_GPIO0Ctrl (1U << 0)
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#define DC_GPIO1Ctrl (1U << 1)
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#define DC_GPIO0 (1U << 2)
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#define DC_GPIO1 (1U << 3)
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#define STGE_AsicCtrl 0x30
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#define AC_ExpRomDisable (1U << 0)
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#define AC_ExpRomSize (1U << 1)
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#define AC_PhySpeed10 (1U << 4)
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#define AC_PhySpeed100 (1U << 5)
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#define AC_PhySpeed1000 (1U << 6)
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#define AC_PhyMedia (1U << 7)
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#define AC_ForcedConfig(x) ((x) << 8)
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#define AC_ForcedConfig_MASK AC_ForcedConfig(7)
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#define AC_D3ResetDisable (1U << 11)
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#define AC_SpeedupMode (1U << 13)
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#define AC_LEDMode (1U << 14)
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#define AC_RstOutPolarity (1U << 15)
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#define AC_GlobalReset (1U << 16)
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#define AC_RxReset (1U << 17)
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#define AC_TxReset (1U << 18)
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#define AC_DMA (1U << 19)
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#define AC_FIFO (1U << 20)
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#define AC_Network (1U << 21)
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#define AC_Host (1U << 22)
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#define AC_AutoInit (1U << 23)
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#define AC_RstOut (1U << 24)
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#define AC_InterruptRequest (1U << 25)
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#define AC_ResetBusy (1U << 26)
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#define AC_LEDSpeed (1U << 27)
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#define AC_LEDModeBit1 (1U << 29)
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#define STGE_FIFOCtrl 0x38 /* 16-bit */
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#define FC_RAMTestMode (1U << 0)
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#define FC_Transmitting (1U << 14)
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#define FC_Receiving (1U << 15)
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#define STGE_RxEarlyThresh 0x3a /* 16-bit */
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#define STGE_FlowOffThresh 0x3c /* 16-bit */
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#define STGE_FlowOnTresh 0x3e /* 16-bit */
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#define STGE_TxStartThresh 0x44 /* 16-bit */
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#define STGE_EepromData 0x48 /* 16-bit */
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#define STGE_EepromCtrl 0x4a /* 16-bit */
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#define EC_EepromAddress(x) ((x) & 0xff)
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#define EC_EepromOpcode(x) ((x) << 8)
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#define EC_OP_WE 0
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#define EC_OP_WR 1
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#define EC_OP_RR 2
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#define EC_OP_ER 3
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#define EC_EepromBusy (1U << 15)
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#define STGE_ExpRomAddr 0x4c
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#define STGE_ExpRomData 0x50 /* 8-bit */
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#define STGE_WakeEvent 0x51 /* 8-bit */
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#define WE_WakePktEnable (1U << 0)
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#define WE_MagicPktEnable (1U << 1)
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#define WE_LinkEventEnable (1U << 2)
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#define WE_WakePolarity (1U << 3)
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#define WE_WakePktEvent (1U << 4)
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#define WE_MagicPktEvent (1U << 5)
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#define WE_LinkEvent (1U << 6)
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#define WE_WakeOnLanEnable (1U << 7)
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#define STGE_Countdown 0x54
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#define CD_Count(x) ((x) & 0xffff)
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#define CD_CountdownSpeed (1U << 24)
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#define CD_CountdownMode (1U << 25)
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#define CD_CountdownIntEnabled (1U << 26)
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#define STGE_IntStatusAck 0x5a /* 16-bit */
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#define STGE_IntEnable 0x5c /* 16-bit */
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#define STGE_IntStatus 0x5e /* 16-bit */
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#define IS_InterruptStatus (1U << 0)
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#define IS_HostError (1U << 1)
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#define IS_TxComplete (1U << 2)
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#define IS_MACControlFrame (1U << 3)
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#define IS_RxComplete (1U << 4)
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#define IS_RxEarly (1U << 5)
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#define IS_InRequested (1U << 6)
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#define IS_UpdateStats (1U << 7)
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#define IS_LinkEvent (1U << 8)
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#define IS_TxDMAComplete (1U << 9)
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#define IS_RxDMAComplete (1U << 10)
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#define IS_RFDListEnd (1U << 11)
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#define IS_RxDMAPriority (1U << 12)
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#define STGE_TxStatus 0x60
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#define TS_TxError (1U << 0)
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#define TS_LateCollision (1U << 2)
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#define TS_MaxCollisions (1U << 3)
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#define TS_TxUnderrun (1U << 4)
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#define TS_TxIndicateReqd (1U << 6)
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#define TS_TxComplete (1U << 7)
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#define TS_TxFrameId_get(x) ((x) >> 16)
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#define STGE_MACCtrl 0x6c
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#define MC_IFSSelect(x) ((x) & 3)
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#define MC_IFS96bit 0
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#define MC_IFS1024bit 1
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#define MC_IFS1792bit 2
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#define MC_IFS4352bit 3
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#define MC_DuplexSelect (1U << 5)
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#define MC_RcvLargeFrames (1U << 6)
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#define MC_TxFlowControlEnable (1U << 7)
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#define MC_RxFlowControlEnable (1U << 8)
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#define MC_RcvFCS (1U << 9)
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#define MC_FIFOLoopback (1U << 10)
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#define MC_MACLoopback (1U << 11)
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#define MC_AutoVLANtagging (1U << 12)
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#define MC_AutoVLANuntagging (1U << 13)
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#define MC_CollisionDetect (1U << 16)
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#define MC_CarrierSense (1U << 17)
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#define MC_StatisticsEnable (1U << 21)
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#define MC_StatisticsDisable (1U << 22)
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#define MC_StatisticsEnabled (1U << 23)
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#define MC_TxEnable (1U << 24)
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#define MC_TxDisable (1U << 25)
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#define MC_TxEnabled (1U << 26)
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#define MC_RxEnable (1U << 27)
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#define MC_RxDisable (1U << 28)
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#define MC_RxEnabled (1U << 29)
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#define MC_Paused (1U << 30)
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#define MC_MASK 0x7fe33fa3
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#define STGE_VLANTag 0x70
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#define STGE_PhySet 0x75 /* 8-bit */
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#define PS_MemLenb9b (1U << 0)
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#define PS_MemLen (1U << 1)
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#define PS_NonCompdet (1U << 2)
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#define STGE_PhyCtrl 0x76 /* 8-bit */
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#define PC_MgmtClk (1U << 0)
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#define PC_MgmtData (1U << 1)
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#define PC_MgmtDir (1U << 2) /* MAC->PHY */
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#define PC_PhyDuplexPolarity (1U << 3)
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#define PC_PhyDuplexStatus (1U << 4)
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#define PC_PhyLnkPolarity (1U << 5)
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#define PC_LinkSpeed(x) (((x) >> 6) & 3)
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#define PC_LinkSpeed_Down 0
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#define PC_LinkSpeed_10 1
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#define PC_LinkSpeed_100 2
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#define PC_LinkSpeed_1000 3
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#define STGE_StationAddress0 0x78 /* 16-bit */
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#define STGE_StationAddress1 0x7a /* 16-bit */
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#define STGE_StationAddress2 0x7c /* 16-bit */
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#define STGE_VLANHashTable 0x7e /* 16-bit */
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#define STGE_VLANId 0x80
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#define STGE_MaxFrameSize 0x86
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#define STGE_ReceiveMode 0x88 /* 16-bit */
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#define RM_ReceiveUnicast (1U << 0)
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#define RM_ReceiveMulticast (1U << 1)
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#define RM_ReceiveBroadcast (1U << 2)
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#define RM_ReceiveAllFrames (1U << 3)
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#define RM_ReceiveMulticastHash (1U << 4)
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#define RM_ReceiveIPMulticast (1U << 5)
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#define RM_ReceiveVLANMatch (1U << 8)
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#define RM_ReceiveVLANHash (1U << 9)
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#define STGE_HashTable0 0x8c
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#define STGE_HashTable1 0x90
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#define STGE_RMONStatisticsMask 0x98 /* set to disable */
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#define STGE_StatisticsMask 0x9c /* set to disable */
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#define STGE_RxJumboFrames 0xbc /* 16-bit */
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#define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */
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#define STGE_IPCheckSumErrors 0xc2 /* 16-bit */
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#define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */
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#define STGE_TxJumboFrames 0xf4 /* 16-bit */
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/*
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* TC9021 statistics. Available memory and I/O mapped.
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*/
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#define STGE_OctetRcvOk 0xa8
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#define STGE_McstOctetRcvdOk 0xac
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#define STGE_BcstOctetRcvdOk 0xb0
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#define STGE_FramesRcvdOk 0xb4
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#define STGE_McstFramesRcvdOk 0xb8
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#define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */
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#define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */
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#define STGE_FrameTooLongErrors 0xc8 /* 16-bit */
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#define STGE_InRangeLengthErrors 0xca /* 16-bit */
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#define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */
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#define STGE_FramesLostRxErrors 0xce /* 16-bit */
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#define STGE_OctetXmtdOk 0xd0
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#define STGE_McstOctetXmtdOk 0xd4
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#define STGE_BcstOctetXmtdOk 0xd8
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#define STGE_FramesXmtdOk 0xdc
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#define STGE_McstFramesXmtdOk 0xe0
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#define STGE_FramesWDeferredXmt 0xe4
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#define STGE_LateCollisions 0xe8
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#define STGE_MultiColFrames 0xec
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#define STGE_SingleColFrames 0xf0
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#define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */
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#define STGE_CarrierSenseErrors 0xf8 /* 16-bit */
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#define STGE_MacControlFramesXmtd 0xfa /* 16-bit */
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#define STGE_FramesAbortXSColls 0xfc /* 16-bit */
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#define STGE_FramesWEXDeferal 0xfe /* 16-bit */
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/*
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* RMON-compatible statistics. Only accessible if memory-mapped.
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*/
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#define STGE_EtherStatsCollisions 0x100
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#define STGE_EtherStatsOctetsTransmit 0x104
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#define STGE_EtherStatsPktsTransmit 0x108
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#define STGE_EtherStatsPkts64OctetsTransmit 0x10c
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#define STGE_EtherStatsPkts64to127OctetsTransmit 0x110
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#define STGE_EtherStatsPkts128to255OctetsTransmit 0x114
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#define STGE_EtherStatsPkts256to511OctetsTransmit 0x118
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#define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c
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#define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120
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#define STGE_EtherStatsCRCAlignErrors 0x124
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#define STGE_EtherStatsUndersizePkts 0x128
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#define STGE_EtherStatsFragments 0x12c
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#define STGE_EtherStatsJabbers 0x130
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#define STGE_EtherStatsOctets 0x134
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#define STGE_EtherStatsPkts 0x138
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#define STGE_EtherStatsPkts64Octets 0x13c
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#define STGE_EtherStatsPkts65to127Octets 0x140
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#define STGE_EtherStatsPkts128to255Octets 0x144
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#define STGE_EtherStatsPkts256to511Octets 0x148
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#define STGE_EtherStatsPkts512to1023Octets 0x14c
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#define STGE_EtherStatsPkts1024to1518Octets 0x150
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/*
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* Transmit descriptor list size.
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*/
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#define STGE_TX_RING_CNT 256
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#define STGE_TX_LOWAT (STGE_TX_RING_CNT/32)
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#define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT)
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/*
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* Receive descriptor list size.
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*/
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#define STGE_RX_RING_CNT 256
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#define STGE_MAXTXSEGS STGE_NTXFRAGS
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#define STGE_JUMBO_FRAMELEN 9022
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#define STGE_JUMBO_MTU \
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(STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
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struct stge_txdesc {
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struct mbuf *tx_m; /* head of our mbuf chain */
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bus_dmamap_t tx_dmamap; /* our DMA map */
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STAILQ_ENTRY(stge_txdesc) tx_q;
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};
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STAILQ_HEAD(stge_txdq, stge_txdesc);
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struct stge_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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};
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#define STGE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
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#define STGE_ADDR_HI(x) ((u_int64_t) (x) >> 32)
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#define STGE_RING_ALIGN 8
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struct stge_chain_data{
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bus_dma_tag_t stge_parent_tag;
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bus_dma_tag_t stge_tx_tag;
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struct stge_txdesc stge_txdesc[STGE_TX_RING_CNT];
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struct stge_txdq stge_txfreeq;
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struct stge_txdq stge_txbusyq;
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bus_dma_tag_t stge_rx_tag;
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struct stge_rxdesc stge_rxdesc[STGE_RX_RING_CNT];
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bus_dma_tag_t stge_tx_ring_tag;
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bus_dmamap_t stge_tx_ring_map;
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bus_dma_tag_t stge_rx_ring_tag;
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bus_dmamap_t stge_rx_ring_map;
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bus_dmamap_t stge_rx_sparemap;
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int stge_tx_prod;
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int stge_tx_cons;
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int stge_tx_cnt;
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int stge_rx_cons;
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#ifdef DEVICE_POLLING
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int stge_rxcycles;
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#endif
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int stge_rxlen;
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struct mbuf *stge_rxhead;
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struct mbuf *stge_rxtail;
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};
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struct stge_ring_data {
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struct stge_tfd *stge_tx_ring;
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bus_addr_t stge_tx_ring_paddr;
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struct stge_rfd *stge_rx_ring;
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bus_addr_t stge_rx_ring_paddr;
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};
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#define STGE_TX_RING_ADDR(sc, i) \
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((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i))
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#define STGE_RX_RING_ADDR(sc, i) \
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((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i))
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#define STGE_TX_RING_SZ \
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(sizeof(struct stge_tfd) * STGE_TX_RING_CNT)
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#define STGE_RX_RING_SZ \
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(sizeof(struct stge_rfd) * STGE_RX_RING_CNT)
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|
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/*
|
|
* Software state per device.
|
|
*/
|
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struct stge_softc {
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if_t sc_ifp; /* interface info */
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device_t sc_dev;
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device_t sc_miibus;
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struct resource *sc_res[2];
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struct resource_spec *sc_spec;
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void *sc_ih; /* interrupt cookie */
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int sc_rev; /* silicon revision */
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struct callout sc_tick_ch; /* tick callout */
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struct stge_chain_data sc_cdata;
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struct stge_ring_data sc_rdata;
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int sc_if_flags;
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int sc_if_framesize;
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int sc_txthresh; /* Tx threshold */
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uint32_t sc_usefiber:1; /* if we're fiber */
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uint32_t sc_stge1023:1; /* are we a 1023 */
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uint32_t sc_DMACtrl; /* prototype DMACtrl reg. */
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uint32_t sc_MACCtrl; /* prototype MacCtrl reg. */
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uint16_t sc_IntEnable; /* prototype IntEnable reg. */
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uint16_t sc_led; /* LED conf. from EEPROM */
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uint8_t sc_PhyCtrl; /* prototype PhyCtrl reg. */
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int sc_suspended;
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|
int sc_detach;
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|
|
int sc_rxint_nframe;
|
|
int sc_rxint_dmawait;
|
|
int sc_nerr;
|
|
int sc_watchdog_timer;
|
|
int sc_link;
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|
|
struct task sc_link_task;
|
|
struct mtx sc_mii_mtx; /* MII mutex */
|
|
struct mtx sc_mtx;
|
|
};
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|
#define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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|
#define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
|
|
#define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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|
#define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx)
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|
#define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx)
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|
|
#define STGE_MAXERR 5
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|
|
#define STGE_RXCHAIN_RESET(_sc) \
|
|
do { \
|
|
(_sc)->sc_cdata.stge_rxhead = NULL; \
|
|
(_sc)->sc_cdata.stge_rxtail = NULL; \
|
|
(_sc)->sc_cdata.stge_rxlen = 0; \
|
|
} while (/*CONSTCOND*/0)
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|
|
#define STGE_TIMEOUT 1000
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|
|
#define STGE_RESET_NONE 0x00
|
|
#define STGE_RESET_TX 0x01
|
|
#define STGE_RESET_RX 0x02
|
|
#define STGE_RESET_FULL 0x04
|