mirror of
https://github.com/freebsd/freebsd-src
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277 lines
7.6 KiB
C
277 lines
7.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2013-2014 Qlogic Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* File: qls_dump.h
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*/
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#ifndef _QLS_DUMP_H_
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#define _QLS_DUMP_H_
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#define Q81_MPID_COOKIE 0x5555aaaa
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typedef struct qls_mpid_glbl_hdr
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{
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uint32_t cookie;
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uint8_t id[16];
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uint32_t time_lo;
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uint32_t time_hi;
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uint32_t img_size;
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uint32_t hdr_size;
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uint8_t info[220];
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} qls_mpid_glbl_hdr_t;
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typedef struct qls_mpid_seg_hdr
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{
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uint32_t cookie;
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uint32_t seg_num;
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uint32_t seg_size;
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uint32_t extra;
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uint8_t desc[16];
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} qls_mpid_seg_hdr_t;
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enum
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{
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Q81_MPI_CORE_REGS_ADDR = 0x00030000,
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Q81_MPI_CORE_REGS_CNT = 127,
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Q81_MPI_CORE_SH_REGS_CNT = 16,
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Q81_TEST_REGS_ADDR = 0x00001000,
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Q81_TEST_REGS_CNT = 23,
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Q81_RMII_REGS_ADDR = 0x00001040,
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Q81_RMII_REGS_CNT = 64,
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Q81_FCMAC1_REGS_ADDR = 0x00001080,
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Q81_FCMAC2_REGS_ADDR = 0x000010c0,
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Q81_FCMAC_REGS_CNT = 64,
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Q81_FC1_MBX_REGS_ADDR = 0x00001100,
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Q81_FC2_MBX_REGS_ADDR = 0x00001240,
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Q81_FC_MBX_REGS_CNT = 64,
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Q81_IDE_REGS_ADDR = 0x00001140,
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Q81_IDE_REGS_CNT = 64,
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Q81_NIC1_MBX_REGS_ADDR = 0x00001180,
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Q81_NIC2_MBX_REGS_ADDR = 0x00001280,
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Q81_NIC_MBX_REGS_CNT = 64,
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Q81_SMBUS_REGS_ADDR = 0x00001200,
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Q81_SMBUS_REGS_CNT = 64,
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Q81_I2C_REGS_ADDR = 0x00001fc0,
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Q81_I2C_REGS_CNT = 64,
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Q81_MEMC_REGS_ADDR = 0x00003000,
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Q81_MEMC_REGS_CNT = 256,
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Q81_PBUS_REGS_ADDR = 0x00007c00,
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Q81_PBUS_REGS_CNT = 256,
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Q81_MDE_REGS_ADDR = 0x00010000,
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Q81_MDE_REGS_CNT = 6,
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Q81_CODE_RAM_ADDR = 0x00020000,
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Q81_CODE_RAM_CNT = 0x2000,
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Q81_MEMC_RAM_ADDR = 0x00100000,
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Q81_MEMC_RAM_CNT = 0x2000,
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Q81_XGMAC_REGISTER_END = 0x740,
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};
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#define Q81_PROBE_DATA_LENGTH_WORDS ((64*2) + 1)
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#define Q81_NUMBER_OF_PROBES 34
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#define Q81_PROBE_SIZE \
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(Q81_PROBE_DATA_LENGTH_WORDS * Q81_NUMBER_OF_PROBES)
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#define Q81_NUMBER_ROUTING_REG_ENTRIES 48
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#define Q81_WORDS_PER_ROUTING_REG_ENTRY 4
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#define Q81_ROUT_REG_SIZE \
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(Q81_NUMBER_ROUTING_REG_ENTRIES * Q81_WORDS_PER_ROUTING_REG_ENTRY)
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#define Q81_MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) +\
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(4096 * 1) + (4 * 2) +\
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(8 * 2) + (16 * 1) +\
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(4 * 1) + (4 * 4) + (4 * 1))
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#define Q81_WORDS_PER_MAC_PROT_ENTRY 2
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#define Q81_MAC_REG_SIZE \
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(Q81_MAC_PROTOCOL_REGISTER_WORDS * Q81_WORDS_PER_MAC_PROT_ENTRY)
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#define Q81_MAX_SEMAPHORE_FUNCTIONS 5
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#define Q81_WQC_WORD_SIZE 6
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#define Q81_NUMBER_OF_WQCS 128
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#define Q81_WQ_SIZE (Q81_WQC_WORD_SIZE * Q81_NUMBER_OF_WQCS)
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#define Q81_CQC_WORD_SIZE 13
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#define Q81_NUMBER_OF_CQCS 128
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#define Q81_CQ_SIZE (Q81_CQC_WORD_SIZE * Q81_NUMBER_OF_CQCS)
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struct qls_mpi_coredump {
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qls_mpid_glbl_hdr_t mpi_global_header;
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qls_mpid_seg_hdr_t core_regs_seg_hdr;
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uint32_t mpi_core_regs[Q81_MPI_CORE_REGS_CNT];
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uint32_t mpi_core_sh_regs[Q81_MPI_CORE_SH_REGS_CNT];
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qls_mpid_seg_hdr_t test_logic_regs_seg_hdr;
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uint32_t test_logic_regs[Q81_TEST_REGS_CNT];
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qls_mpid_seg_hdr_t rmii_regs_seg_hdr;
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uint32_t rmii_regs[Q81_RMII_REGS_CNT];
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qls_mpid_seg_hdr_t fcmac1_regs_seg_hdr;
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uint32_t fcmac1_regs[Q81_FCMAC_REGS_CNT];
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qls_mpid_seg_hdr_t fcmac2_regs_seg_hdr;
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uint32_t fcmac2_regs[Q81_FCMAC_REGS_CNT];
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qls_mpid_seg_hdr_t fc1_mbx_regs_seg_hdr;
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uint32_t fc1_mbx_regs[Q81_FC_MBX_REGS_CNT];
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qls_mpid_seg_hdr_t ide_regs_seg_hdr;
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uint32_t ide_regs[Q81_IDE_REGS_CNT];
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qls_mpid_seg_hdr_t nic1_mbx_regs_seg_hdr;
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uint32_t nic1_mbx_regs[Q81_NIC_MBX_REGS_CNT];
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qls_mpid_seg_hdr_t smbus_regs_seg_hdr;
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uint32_t smbus_regs[Q81_SMBUS_REGS_CNT];
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qls_mpid_seg_hdr_t fc2_mbx_regs_seg_hdr;
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uint32_t fc2_mbx_regs[Q81_FC_MBX_REGS_CNT];
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qls_mpid_seg_hdr_t nic2_mbx_regs_seg_hdr;
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uint32_t nic2_mbx_regs[Q81_NIC_MBX_REGS_CNT];
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qls_mpid_seg_hdr_t i2c_regs_seg_hdr;
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uint32_t i2c_regs[Q81_I2C_REGS_CNT];
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qls_mpid_seg_hdr_t memc_regs_seg_hdr;
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uint32_t memc_regs[Q81_MEMC_REGS_CNT];
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qls_mpid_seg_hdr_t pbus_regs_seg_hdr;
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uint32_t pbus_regs[Q81_PBUS_REGS_CNT];
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qls_mpid_seg_hdr_t mde_regs_seg_hdr;
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uint32_t mde_regs[Q81_MDE_REGS_CNT];
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qls_mpid_seg_hdr_t xaui1_an_hdr;
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uint32_t serdes1_xaui_an[14];
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qls_mpid_seg_hdr_t xaui1_hss_pcs_hdr;
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uint32_t serdes1_xaui_hss_pcs[33];
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qls_mpid_seg_hdr_t xfi1_an_hdr;
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uint32_t serdes1_xfi_an[14];
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qls_mpid_seg_hdr_t xfi1_train_hdr;
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uint32_t serdes1_xfi_train[12];
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qls_mpid_seg_hdr_t xfi1_hss_pcs_hdr;
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uint32_t serdes1_xfi_hss_pcs[15];
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qls_mpid_seg_hdr_t xfi1_hss_tx_hdr;
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uint32_t serdes1_xfi_hss_tx[32];
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qls_mpid_seg_hdr_t xfi1_hss_rx_hdr;
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uint32_t serdes1_xfi_hss_rx[32];
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qls_mpid_seg_hdr_t xfi1_hss_pll_hdr;
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uint32_t serdes1_xfi_hss_pll[32];
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qls_mpid_seg_hdr_t xaui2_an_hdr;
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uint32_t serdes2_xaui_an[14];
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qls_mpid_seg_hdr_t xaui2_hss_pcs_hdr;
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uint32_t serdes2_xaui_hss_pcs[33];
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qls_mpid_seg_hdr_t xfi2_an_hdr;
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uint32_t serdes2_xfi_an[14];
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qls_mpid_seg_hdr_t xfi2_train_hdr;
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uint32_t serdes2_xfi_train[12];
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qls_mpid_seg_hdr_t xfi2_hss_pcs_hdr;
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uint32_t serdes2_xfi_hss_pcs[15];
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qls_mpid_seg_hdr_t xfi2_hss_tx_hdr;
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uint32_t serdes2_xfi_hss_tx[32];
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qls_mpid_seg_hdr_t xfi2_hss_rx_hdr;
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uint32_t serdes2_xfi_hss_rx[32];
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qls_mpid_seg_hdr_t xfi2_hss_pll_hdr;
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uint32_t serdes2_xfi_hss_pll[32];
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qls_mpid_seg_hdr_t nic1_regs_seg_hdr;
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uint32_t nic1_regs[64];
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qls_mpid_seg_hdr_t nic2_regs_seg_hdr;
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uint32_t nic2_regs[64];
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qls_mpid_seg_hdr_t intr_states_seg_hdr;
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uint32_t intr_states[MAX_RX_RINGS];
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qls_mpid_seg_hdr_t xgmac1_seg_hdr;
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uint32_t xgmac1[Q81_XGMAC_REGISTER_END];
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qls_mpid_seg_hdr_t xgmac2_seg_hdr;
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uint32_t xgmac2[Q81_XGMAC_REGISTER_END];
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qls_mpid_seg_hdr_t probe_dump_seg_hdr;
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uint32_t probe_dump[Q81_PROBE_SIZE];
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qls_mpid_seg_hdr_t routing_reg_seg_hdr;
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uint32_t routing_regs[Q81_ROUT_REG_SIZE];
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qls_mpid_seg_hdr_t mac_prot_reg_seg_hdr;
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uint32_t mac_prot_regs[Q81_MAC_REG_SIZE];
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qls_mpid_seg_hdr_t sem_regs_seg_hdr;
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uint32_t sem_regs[Q81_MAX_SEMAPHORE_FUNCTIONS];
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qls_mpid_seg_hdr_t ets_seg_hdr;
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uint32_t ets[8+2];
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qls_mpid_seg_hdr_t wqc1_seg_hdr;
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uint32_t wqc1[Q81_WQ_SIZE];
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qls_mpid_seg_hdr_t cqc1_seg_hdr;
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uint32_t cqc1[Q81_CQ_SIZE];
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qls_mpid_seg_hdr_t wqc2_seg_hdr;
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uint32_t wqc2[Q81_WQ_SIZE];
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qls_mpid_seg_hdr_t cqc2_seg_hdr;
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uint32_t cqc2[Q81_CQ_SIZE];
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qls_mpid_seg_hdr_t code_ram_seg_hdr;
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uint32_t code_ram[Q81_CODE_RAM_CNT];
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qls_mpid_seg_hdr_t memc_ram_seg_hdr;
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uint32_t memc_ram[Q81_MEMC_RAM_CNT];
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};
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typedef struct qls_mpi_coredump qls_mpi_coredump_t;
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#define Q81_BAD_DATA 0xDEADBEEF
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#endif /* #ifndef _QLS_DUMP_H_ */
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