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528 lines
12 KiB
C
528 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This is a pinmux/gpio controller for the IPQ4018/IPQ4019.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include "qcom_tlmm_var.h"
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#include "qcom_tlmm_ipq4018_reg.h"
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#include "qcom_tlmm_ipq4018_hw.h"
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#include "gpio_if.h"
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/*
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* Set the pin function. This is a hardware and pin specific mapping.
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*
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* Returns 0 if OK, an errno if an error was encountered.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_set_function(struct qcom_tlmm_softc *sc,
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int pin, int function)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT);
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reg |= (function & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK)
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT;
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GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
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return (0);
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}
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/*
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* Get the pin function. This is a hardware and pin specific mapping.
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*
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* Returns 0 if OK, an errno if a nerror was encountered.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_get_function(struct qcom_tlmm_softc *sc,
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int pin, int *function)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg = reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT;
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reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK;
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*function = reg;
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return (0);
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}
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/*
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* Set the OE bit to be output. This assumes the port is configured
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* as a GPIO port.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_set_oe_output(struct qcom_tlmm_softc *sc,
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int pin)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;
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GPIO_WRITE(sc,
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QCOM_TLMM_IPQ4018_REG_PIN(pin, QCOM_TLMM_IPQ4018_REG_PIN_CONTROL),
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reg);
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return (0);
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}
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/*
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* Set the OE bit to be input. This assumes the port is configured
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* as a GPIO port.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_set_oe_input(struct qcom_tlmm_softc *sc,
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int pin)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;
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GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
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return (0);
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}
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/*
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* Get the GPIO pin direction. is_output is set to true if the pin
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* is an output pin, false if it's set to an input pin.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_get_oe_state(struct qcom_tlmm_softc *sc,
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int pin, bool *is_output)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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*is_output = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE);
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return (0);
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}
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/*
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* Set the given GPIO pin to the given value.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_set_output_value(struct qcom_tlmm_softc *sc,
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uint32_t pin, unsigned int value)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_IO));
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if (value)
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
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else
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reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
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GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);
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return (0);
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}
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/*
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* Get the input state of the current GPIO pin.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_get_output_value(struct qcom_tlmm_softc *sc,
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uint32_t pin, unsigned int *val)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_IO));
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*val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);
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return (0);
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}
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/*
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* Get the input state of the current GPIO pin.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_get_input_value(struct qcom_tlmm_softc *sc,
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uint32_t pin, unsigned int *val)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_IO));
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*val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);
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return (0);
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}
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/*
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* Toggle the current output pin value.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_toggle_output_value(
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struct qcom_tlmm_softc *sc, uint32_t pin)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_IO));
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if ((reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN) == 0)
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
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else
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reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
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GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);
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return (0);
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}
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/*
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* Configure the pull-up / pull-down top-level configuration.
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*
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* This doesn't configure the resistor values, just what's enabled/disabled.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_set_pupd_config(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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qcom_tlmm_pin_pupd_config_t pupd)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT);
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switch (pupd) {
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case QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE:
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
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break;
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case QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN:
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
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break;
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case QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP:
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
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break;
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case QCOM_TLMM_PIN_PUPD_CONFIG_BUS_HOLD:
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_BUSHOLD
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
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break;
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}
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GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
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return (0);
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}
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/*
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* Fetch the current pull-up / pull-down configuration.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_get_pupd_config(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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qcom_tlmm_pin_pupd_config_t *pupd)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg >>= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
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reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK;
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switch (reg) {
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case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE:
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*pupd = QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE;
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break;
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case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN:
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*pupd = QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN;
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break;
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case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP:
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*pupd = QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP;
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break;
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default:
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*pupd = QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE;
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break;
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}
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return (0);
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}
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/*
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* Set the drive strength in mA.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_set_drive_strength(
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struct qcom_tlmm_softc *sc, uint32_t pin, uint8_t drv)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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/* Convert mA to hardware */
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if (drv > 16 || drv < 2)
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return (EINVAL);
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drv = (drv / 2) - 1;
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK);
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reg |= (drv & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK)
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<< QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT;
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GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
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return (0);
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}
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/*
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* Get the drive strength in mA.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_get_drive_strength(
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struct qcom_tlmm_softc *sc, uint32_t pin, uint8_t *drv)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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*drv = (reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT)
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& QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK;
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*drv = (*drv + 1) * 2;
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return (0);
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}
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/*
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* Enable/disable whether this pin is passed through to a VM.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_set_vm(
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struct qcom_tlmm_softc *sc, uint32_t pin, bool enable)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;
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if (enable)
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reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;
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GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
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return (0);
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}
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/*
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* Get the VM configuration bit.
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*/
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int
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qcom_tlmm_ipq4018_hw_pin_get_vm(
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struct qcom_tlmm_softc *sc, uint32_t pin, bool *enable)
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{
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uint32_t reg;
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GPIO_LOCK_ASSERT(sc);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
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QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
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*enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE);
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return (0);
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|
}
|
|
|
|
/*
|
|
* Enable/disable open drain.
|
|
*/
|
|
int
|
|
qcom_tlmm_ipq4018_hw_pin_set_open_drain(
|
|
struct qcom_tlmm_softc *sc, uint32_t pin, bool enable)
|
|
{
|
|
uint32_t reg;
|
|
|
|
GPIO_LOCK_ASSERT(sc);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
|
|
QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
|
|
|
|
reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;
|
|
if (enable)
|
|
reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;
|
|
|
|
GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
|
|
QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Get the open drain configuration bit.
|
|
*/
|
|
int
|
|
qcom_tlmm_ipq4018_hw_pin_get_open_drain(
|
|
struct qcom_tlmm_softc *sc, uint32_t pin, bool *enable)
|
|
{
|
|
uint32_t reg;
|
|
|
|
GPIO_LOCK_ASSERT(sc);
|
|
|
|
if (pin >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
|
|
QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
|
|
|
|
*enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE);
|
|
|
|
return (0);
|
|
}
|