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396 lines
13 KiB
C
396 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This is a pinmux/gpio controller for the IPQ4018/IPQ4019.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include "qcom_tlmm_var.h"
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#include "qcom_tlmm_pin.h"
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#include "qcom_tlmm_debug.h"
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#include "qcom_tlmm_ipq4018_reg.h"
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#include "qcom_tlmm_ipq4018_hw.h"
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#include "gpio_if.h"
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#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
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/* 100 GPIO pins, 0..99 */
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#define QCOM_TLMM_IPQ4018_GPIO_PINS 100
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static const struct qcom_tlmm_gpio_mux gpio_muxes[] = {
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GDEF(0, "jtag_tdi", "smart0", "i2s_rx_bclk"),
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GDEF(1, "jtag_tck", "smart0", "i2s_rx_fsync"),
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GDEF(2, "jtag_tms", "smart0", "i2s_rxd"),
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GDEF(3, "jtag_tdo"),
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GDEF(4, "jtag_rst"),
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GDEF(5, "jtag_trst"),
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GDEF(6, "mdio0", NULL, "wcss0_dbg18", "wcss1_dbg18", NULL,
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"qdss_tracedata_a"),
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GDEF(7, "mdc", NULL, "wcss0_dbg19", "wcss1_dbg19", NULL,
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"qdss_tracedata_a"),
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GDEF(8, "blsp_uart1", "wifi0_uart", "wifi1_uart", "smart1", NULL,
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"wcss0_dbg20", "wcss1_dbg20", NULL, "qdss_tracedata_a"),
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GDEF(9, "blsp_uart1", "wifi0_uart0", "wifi1_uart0", "smart1",
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"wifi0_uart", NULL, "wcss0_dbg21", "wcss1_dbg21", NULL,
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"qdss_tracedata_a"),
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GDEF(10, "blsp_uart1", "wifi0_uart0", "wifi1_uart0", "blsp_i2c0",
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NULL, "wcss0_dbg22", "wcss1_dbg22", NULL, "qdss_tracedata_a"),
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GDEF(11, "blsp_uart1", "wifi0_uart", "wifi1_uart", "blsp_i2c0",
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NULL, "wcss0_dbg23", "wcss1_dbg23", NULL, "qdss_tracedata_a"),
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GDEF(12, "blsp_spi0", "blsp_i2c1", NULL, "wcss0_dbg24",
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"wcss1_dbg24"),
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GDEF(13, "blsp_spi0", "blsp_i2c1", NULL, "wcss0_dbg25",
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"wcss1_dbg25"),
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GDEF(14, "blsp_spi0", NULL, "wcss0_dbg26", "wcss1_dbg26"),
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GDEF(15, "blsp_spi0", NULL, "wcss0_dbg", "wcss1_dbg"),
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GDEF(16, "blsp_uart0", "led0", "smart1", NULL, "wcss0_dbg28",
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"wcss1_dbg28", NULL, "qdss_tracedata_a"),
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GDEF(17, "blsp_uart0", "led1", "smart1", NULL, "wcss0_dbg29",
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"wcss1_dbg29", NULL, "qdss_tracedata_a"),
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GDEF(18, "wifi0_uart1", "wifi1_uart1", NULL, "wcss0_dbg30",
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"wcss1_dbg30"),
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GDEF(19, "wifi0_uart", "wifi1_uart", NULL, "wcss0_dbg31",
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"wcss1_dbg31"),
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GDEF(20, "blsp_i2c0", "i2s_rx_mclk", NULL, "wcss0_dbg16",
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"wcss1_dbg16"),
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GDEF(21, "blsp_i2c0", "i2s_rx_bclk", NULL, "wcss0_dbg17",
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"wcss1_dbg17"),
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GDEF(22, "rgmii0", "i2s_rx_fsync", NULL, "wcss0_dbg18",
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"wcss1_dbg18"),
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GDEF(23, "sdio0", "rgmii1", "i2s_rxd", NULL, "wcss0_dbg19",
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"wcss1_dbg19"),
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GDEF(24, "sdio1", "rgmii2", "i2s_tx_mclk", NULL, "wcss0_dbg20",
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"wcss1_dbg20"),
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GDEF(25, "sdio2", "rgmii3", "i2s_tx_bclk", NULL, "wcss0_dbg21",
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"wcss1_dbg21"),
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GDEF(26, "sdio3", "rgmii_rx", "i2s_tx_fsync", NULL, "wcss0_dbg22",
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"wcss1_dbg22"),
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GDEF(27, "sdio_clk", "rgmii_txc", "i2s_tdl", NULL, "wcss0_dbg23",
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"wcss1_dbg23"),
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GDEF(28, "sdio_cmd", "rgmii0", "i2s_td2", NULL, "wcss0_dbg24",
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"wcss1_dbg24"),
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GDEF(29, "sdio4", "rgmii1", "i2s_td3", NULL, "wcss0_dbg25",
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"wcss1_dbg25"),
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GDEF(30, "sdio5", "rgmii2", "audio_pwm0", NULL, "wcss0_dbg26",
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"wcss1_dbg26"),
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GDEF(31, "sdio6", "rgmii3", "audio_pwm1", NULL, "wcss0_dbg27",
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"wcss1_dbg27"),
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GDEF(32, "sdio7", "rgmii_rxc", "audio_pwm2", NULL, "wcss0_dbg28",
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"wcss1_dbg28"),
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GDEF(33, "rgmii_tx", "audio_pwm3", NULL, "wcss0_dbg29",
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"wcss1_dbg29", NULL, "boot2"),
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GDEF(34, "blsp_i2c1", "i2s_spdif_in", NULL, "wcss0_dbg30",
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"wcss1_dbg30"),
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GDEF(35, "blsp_i2c1", "i2s_spdif_out", NULL, "wcss0_dbg31",
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"wcss1_dbg31"),
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GDEF(36, "rmii00", "led2", "led0"),
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GDEF(37, "rmii01", "wifi0_wci", "wifi1_wci", "led1", NULL, NULL,
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"wcss0_dbg16", "wcss1_dbg16", NULL, "qdss_tracedata_a", "boot4"),
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GDEF(38, "rmii0_tx", "led2", NULL, NULL, "wcss0_dbg17",
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"wcss1_dbg17", NULL, "qdss_tracedata_a", "boot5"),
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GDEF(39, "rmii0_rx", "pcie_clk1", "led3", NULL, NULL, "wcss0_dbg18",
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"wcss1_dbg18", NULL, NULL, "qdss_tracedata_a"),
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GDEF(40, "rmii0_refclk", "wifi0_rfsilent0", "wifi1_rfsilent0",
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"smart2", "led4", NULL, NULL, "wcss0_dbg19", "wcss1_dbg19", NULL,
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NULL, "qdss_tracedata_a"),
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GDEF(41, "rmii00", "wifi0_cal", "wifi1_cal", "smart2", NULL, NULL,
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"wcss0_dbg20", "wcss1_dbg20", NULL, NULL, "qdss_tracedata_a"),
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GDEF(42, "rmii01", "wifi_wci0", NULL, NULL, "wcss0_dbg21",
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"wcss1_dbg21", NULL, NULL, "qdss_tracedata_a"),
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GDEF(43, "rmii0_dv", "wifi_wci1", NULL, NULL, "wcss0_dbg22",
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"wcss1_dbg22", NULL, NULL, "qdss_tracedata_a"),
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GDEF(44, "rmii1_refclk", "blsp_spi1", "smart0", "led5", NULL, NULL,
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"wcss0_dbg23", "wcss1_dbg23"),
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GDEF(45, "rmii10", "blsp_spi1", "smart0", "led6", NULL, NULL,
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"wcss0_dbg24", "wcss1_dbg24"),
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GDEF(46, "rmii11", "blsp_spi1", "smart0", "led7", NULL, NULL,
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"wcss0_dbg25", "wcss1_dbg25"),
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GDEF(47, "rmii1_dv", "blsp_spi1", "smart0", "led8", NULL, NULL,
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"wcss0_dbg26", "wcss1_dbg26"),
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GDEF(48, "rmii1_tx", "aud_pin", "smart2", "led9", NULL, NULL,
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"wcss0_dbg27", "wcss1_dbg27"),
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GDEF(49, "rmii1_rx", "aud_pin", "smart2", "led10", NULL, NULL,
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"wcss0_dbg28", "wcss1_dbg28"),
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GDEF(50, "rmii10", "aud_pin", "wifi0_rfsilent1", "wifi1_rfsilent1",
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"led11", NULL, NULL, "wcss0_dbg29", "wcss1_dbg29"),
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GDEF(51, "rmii11", "aud_pin", "wifi0_cal", "wifi1_cal", NULL, NULL,
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"wcss0_dbg30", "wcss1_dbg30", NULL, "boot7"),
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GDEF(52, "qpic_pad", "mdc", "pcie_clk", "i2s_tx_mclk", NULL, NULL,
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"wcss0_dbg31", "tm_clk0", "wifi00", "wifi10"),
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GDEF(53, "qpic_pad", "mdio1", "i2s_tx_bclk", "prng_rsoc", "dbg_out",
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"tm0", "wifi01", "wifi11"),
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GDEF(54, "qpic_pad", "blsp_spi0", "i2s_tdl", "atest_char3", "pmu0",
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NULL, NULL, "boot8", "tm1"),
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GDEF(55, "qpic_pad", "blsp_spi0", "i2s_td2", "atest_char2", "pmu1",
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NULL, NULL, "boot9", "tm2"),
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GDEF(56, "qpic_pad", "blsp_spi0", "i2s_td3", "atest_char1", NULL,
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"tm_ack", "wifi03", "wifi13"),
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GDEF(57, "qpic_pad4", "blsp_spi0", "i2s_tx_fsync", "atest_char0",
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NULL, "tm3", "wifi02", "wifi12"),
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GDEF(58, "qpic_pad5", "led2", "blsp_i2c0", "smart3", "smart1",
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"i2s_rx_mclk", NULL, "wcss0_dbg14", "tm4", "wifi04", "wifi14"),
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GDEF(59, "qpic_pad6", "blsp_i2c0", "smart3", "smart1", "i2c_spdif_in",
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NULL, NULL, "wcss0_dbg15", "qdss_tracectl_a", "boot18", "tm5" ),
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GDEF(60, "qpic_pad7", "blsp_uart0", "smart1", "smart3", "led0",
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"i2s_tx_bclk", "i2s_rx_bclk", "atest_char", NULL, "wcss0_dbg4",
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"qdss_traceclk_a", "boot19", "tm6" ),
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GDEF(61, "qpic_pad", "blsp_uart0", "smart1", "smart3", "led1",
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"i2s_tx_fsync", "i2s_rx_fsync", NULL, NULL, "wcss0_dbg5",
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"qdss_cti_trig_out_a0", "boot14", "tm7"),
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GDEF(62, "qpic_pad", "chip_rst", "wifi0_uart", "wifi1_uart",
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"i2s_spdif_out", NULL, NULL, "wcss0_dbg6", "qdss_cti_trig_out_b0",
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"boot11", "tm8"),
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GDEF(63, "qpic_pad", "wifi0_uart1", "wifi1_uart1", "wifi1_uart",
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"i2s_tdl", "i2s_rxd", "i2s_spdif_out", "i2s_spdif_in", NULL,
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"wcss0_dbg7", "wcss1_dbg7", "boot20", "tm9"),
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GDEF(64, "qpic_pad1", "audio_pwm0", NULL, "wcss0_dbg8", "wcss1_dbg8"),
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GDEF(65, "qpic_pad2", "audio_pwm1", NULL, "wcss0_dbg9",
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"wcss1_dbg9" ),
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GDEF(66, "qpic_pad3", "audio_pwm2", NULL, "wcss0_dbg10",
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"wcss1_dbg10"),
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GDEF(67, "qpic_pad0", "audio_pwm3", NULL, "wcss0_dbg11",
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"wcss1_dbg11"),
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GDEF(68, "qpic_pad8", NULL, "wcss0_dbg12", "wcss1_dbg12"),
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GDEF(69, "qpic_pad", NULL, "wcss0_dbg"),
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GDEF(70),
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GDEF(71),
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GDEF(72),
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GDEF(73),
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GDEF(74),
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GDEF(75),
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GDEF(76),
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GDEF(77),
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GDEF(78),
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GDEF(79),
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GDEF(80),
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GDEF(81),
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GDEF(82),
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GDEF(83),
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GDEF(84),
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GDEF(85),
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GDEF(86),
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GDEF(87),
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GDEF(88),
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GDEF(89),
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GDEF(90),
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GDEF(91),
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GDEF(92),
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GDEF(93),
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GDEF(94),
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GDEF(95),
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GDEF(96),
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GDEF(97),
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GDEF(98, "wifi034", "wifi134"),
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GDEF(99),
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GDEF(-1),
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};
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static int
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qcom_tlmm_ipq4018_probe(device_t dev)
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{
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if (! ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "qcom,ipq4019-pinctrl") == 0)
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return (ENXIO);
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device_set_desc(dev,
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"Qualcomm Atheross TLMM IPQ4018/IPQ4019 GPIO/Pinmux driver");
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return (0);
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}
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static int
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qcom_tlmm_ipq4018_detach(device_t dev)
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{
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struct qcom_tlmm_softc *sc = device_get_softc(dev);
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KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
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gpiobus_detach_bus(dev);
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if (sc->gpio_ih)
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bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
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if (sc->gpio_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
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sc->gpio_irq_res);
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if (sc->gpio_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
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sc->gpio_mem_res);
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if (sc->gpio_pins)
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free(sc->gpio_pins, M_DEVBUF);
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mtx_destroy(&sc->gpio_mtx);
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return(0);
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}
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static int
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qcom_tlmm_ipq4018_attach(device_t dev)
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{
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struct qcom_tlmm_softc *sc = device_get_softc(dev);
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int i;
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KASSERT((device_get_unit(dev) == 0),
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("qcom_tlmm_ipq4018: Only one gpio module supported"));
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mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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/* Map control/status registers. */
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sc->gpio_mem_rid = 0;
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sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->gpio_mem_rid, RF_ACTIVE);
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if (sc->gpio_mem_res == NULL) {
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device_printf(dev, "couldn't map memory\n");
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qcom_tlmm_ipq4018_detach(dev);
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return (ENXIO);
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}
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if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
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device_printf(dev, "unable to allocate IRQ resource\n");
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qcom_tlmm_ipq4018_detach(dev);
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return (ENXIO);
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}
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if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
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qcom_tlmm_filter, qcom_tlmm_intr, sc, &sc->gpio_ih))) {
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device_printf(dev,
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"WARNING: unable to register interrupt handler\n");
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qcom_tlmm_ipq4018_detach(dev);
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return (ENXIO);
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}
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sc->dev = dev;
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sc->gpio_npins = QCOM_TLMM_IPQ4018_GPIO_PINS;
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sc->gpio_muxes = &gpio_muxes[0];
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sc->sc_debug = 0;
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qcom_tlmm_debug_sysctl_attach(sc);
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/* Allocate local pin state for all of our pins */
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sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
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M_DEVBUF, M_WAITOK | M_ZERO);
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/* Note: direct map between gpio pin and gpio_pin[] entry */
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for (i = 0; i < sc->gpio_npins; i++) {
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snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
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"gpio%d", i);
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sc->gpio_pins[i].gp_pin = i;
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sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
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(void) qcom_tlmm_pin_getflags(dev, i,
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&sc->gpio_pins[i].gp_flags);
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}
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fdt_pinctrl_register(dev, NULL);
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fdt_pinctrl_configure_by_name(dev, "default");
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sc->busdev = gpiobus_attach_bus(dev);
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if (sc->busdev == NULL) {
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device_printf(dev, "%s: failed to attach bus\n", __func__);
|
|
qcom_tlmm_ipq4018_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t qcom_tlmm_ipq4018_methods[] = {
|
|
/* Driver */
|
|
DEVMETHOD(device_probe, qcom_tlmm_ipq4018_probe),
|
|
DEVMETHOD(device_attach, qcom_tlmm_ipq4018_attach),
|
|
DEVMETHOD(device_detach, qcom_tlmm_ipq4018_detach),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, qcom_tlmm_get_bus),
|
|
DEVMETHOD(gpio_pin_max, qcom_tlmm_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, qcom_tlmm_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, qcom_tlmm_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, qcom_tlmm_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, qcom_tlmm_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, qcom_tlmm_pin_get),
|
|
DEVMETHOD(gpio_pin_set, qcom_tlmm_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, qcom_tlmm_pin_toggle),
|
|
|
|
/* OFW */
|
|
DEVMETHOD(ofw_bus_get_node, qcom_tlmm_pin_get_node),
|
|
|
|
/* fdt_pinctrl interface */
|
|
DEVMETHOD(fdt_pinctrl_configure, qcom_tlmm_pinctrl_configure),
|
|
|
|
{0, 0},
|
|
};
|
|
|
|
static driver_t qcom_tlmm_ipq4018_driver = {
|
|
"gpio",
|
|
qcom_tlmm_ipq4018_methods,
|
|
sizeof(struct qcom_tlmm_softc),
|
|
};
|
|
|
|
EARLY_DRIVER_MODULE(qcom_tlmm_ipq4018, simplebus, qcom_tlmm_ipq4018_driver,
|
|
NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|
|
EARLY_DRIVER_MODULE(qcom_tlmm_ipq4018, ofwbus, qcom_tlmm_ipq4018_driver,
|
|
NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|
|
MODULE_VERSION(qcom_tlmm_ipq4018, 1);
|