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177 lines
6.6 KiB
C
177 lines
6.6 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
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/* $NetBSD: qat_c2xxxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
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/*
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* Copyright (c) 2019 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright(c) 2007-2013 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_QAT_C2XXXREG_H_
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#define _DEV_PCI_QAT_C2XXXREG_H_
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/* PCI revision IDs */
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#define QAT_REVID_C2XXX_A0 0x00
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#define QAT_REVID_C2XXX_B0 0x02
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#define QAT_REVID_C2XXX_C0 0x03
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/* Max number of accelerators and engines */
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#define MAX_ACCEL_C2XXX 1
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#define MAX_AE_C2XXX 2
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/* PCIe BAR index */
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#define BAR_SRAM_ID_C2XXX NO_PCI_REG
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#define BAR_PMISC_ID_C2XXX 0
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#define BAR_ETR_ID_C2XXX 1
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#define ACCEL_MASK_C2XXX 0x1
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#define AE_MASK_C2XXX 0x3
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#define MSIX_AE_VEC_GAP_C2XXX 8
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/* PCIe configuration space registers */
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/* PESRAM: 512K eSRAM */
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#define BAR_PESRAM_C2XXX NO_PCI_REG
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#define BAR_PESRAM_SIZE_C2XXX 0
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/*
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* PMISC: 16K CAP, 16K Scratch, 32K SSU(QATs),
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* 32K AE CSRs and transfer registers, 8K CHAP/PMU,
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* 4K EP CSRs, 4K MSI-X Tables
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*/
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#define BAR_PMISC_C2XXX 0x18
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#define BAR_PMISC_SIZE_C2XXX 0x20000 /* 128K */
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/* PETRINGCSR: 8K 16 bundles of ET Ring CSRs */
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#define BAR_PETRINGCSR_C2XXX 0x20
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#define BAR_PETRINGCSR_SIZE_C2XXX 0x4000 /* 16K */
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/* Fuse Control */
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#define FUSECTL_C2XXX_PKE_DISABLE (1 << 6)
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#define FUSECTL_C2XXX_ATH_DISABLE (1 << 5)
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#define FUSECTL_C2XXX_CPH_DISABLE (1 << 4)
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#define FUSECTL_C2XXX_LOW_SKU (1 << 3)
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#define FUSECTL_C2XXX_MID_SKU (1 << 2)
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#define FUSECTL_C2XXX_AE1_DISABLE (1 << 1)
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/* SINT: Signal Target Raw Interrupt Register */
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#define EP_SINTPF_C2XXX 0x1A024
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/* SMIA: Signal Target IA Mask Register */
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#define EP_SMIA_C2XXX 0x1A028
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#define EP_SMIA_BUNDLES_IRQ_MASK_C2XXX 0xFF
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#define EP_SMIA_AE_IRQ_MASK_C2XXX 0x10000
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#define EP_SMIA_MASK_C2XXX \
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(EP_SMIA_BUNDLES_IRQ_MASK_C2XXX | EP_SMIA_AE_IRQ_MASK_C2XXX)
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#define EP_RIMISCCTL_C2XXX 0x1A0C4
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#define EP_RIMISCCTL_MASK_C2XXX 0x40000000
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#define PFCGCIOSFPRIR_REG_C2XXX 0x2C0
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#define PFCGCIOSFPRIR_MASK_C2XXX 0XFFFF7FFF
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/* BAR sub-regions */
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#define PESRAM_BAR_C2XXX NO_PCI_REG
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#define PESRAM_OFFSET_C2XXX 0x0
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#define PESRAM_SIZE_C2XXX 0x0
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#define CAP_GLOBAL_BAR_C2XXX BAR_PMISC_C2XXX
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#define CAP_GLOBAL_OFFSET_C2XXX 0x00000
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#define CAP_GLOBAL_SIZE_C2XXX 0x04000
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#define CAP_HASH_OFFSET 0x900
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#define SCRATCH_BAR_C2XXX NO_PCI_REG
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#define SCRATCH_OFFSET_C2XXX NO_REG_OFFSET
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#define SCRATCH_SIZE_C2XXX 0x0
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#define SSU_BAR_C2XXX BAR_PMISC_C2XXX
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#define SSU_OFFSET_C2XXX 0x08000
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#define SSU_SIZE_C2XXX 0x08000
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#define AE_BAR_C2XXX BAR_PMISC_C2XXX
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#define AE_OFFSET_C2XXX 0x10000
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#define AE_LOCAL_OFFSET_C2XXX 0x10800
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#define PMU_BAR_C2XXX NO_PCI_REG
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#define PMU_OFFSET_C2XXX NO_REG_OFFSET
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#define PMU_SIZE_C2XXX 0x0
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#define EP_BAR_C2XXX BAR_PMISC_C2XXX
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#define EP_OFFSET_C2XXX 0x1A000
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#define EP_SIZE_C2XXX 0x01000
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#define MSIX_TAB_BAR_C2XXX NO_PCI_REG /* mapped by pci(9) */
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#define MSIX_TAB_OFFSET_C2XXX 0x1B000
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#define MSIX_TAB_SIZE_C2XXX 0x01000
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#define PETRINGCSR_BAR_C2XXX BAR_PETRINGCSR_C2XXX
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#define PETRINGCSR_OFFSET_C2XXX 0x0
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#define PETRINGCSR_SIZE_C2XXX 0x0 /* use size of BAR */
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/* ETR */
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#define ETR_MAX_BANKS_C2XXX 8
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#define ETR_MAX_ET_RINGS_C2XXX \
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(ETR_MAX_BANKS_C2XXX * ETR_MAX_RINGS_PER_BANK_C2XXX)
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#define ETR_MAX_AP_BANKS_C2XXX 4
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#define ETR_TX_RX_GAP_C2XXX 1
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#define ETR_TX_RINGS_MASK_C2XXX 0x51
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#define ETR_BUNDLE_SIZE_C2XXX 0x0200
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/* Initial bank Interrupt Source mask */
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#define ETR_INT_SRCSEL_MASK_0_C2XXX 0x4444444CUL
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#define ETR_INT_SRCSEL_MASK_X_C2XXX 0x44444444UL
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/* AE firmware */
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#define AE_FW_PROD_TYPE_C2XXX 0x00800000
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#define AE_FW_MOF_NAME_C2XXX "qat_c2xxxfw"
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#define AE_FW_MMP_NAME_C2XXX "mmp_firmware_c2xxx"
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#define AE_FW_UOF_NAME_C2XXX_A0 "icp_qat_nae.uof"
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#define AE_FW_UOF_NAME_C2XXX_B0 "icp_qat_nae_b0.uof"
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#endif
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