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217 lines
7.2 KiB
C
217 lines
7.2 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
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/* $NetBSD: qat_c2xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
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/*
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* Copyright (c) 2019 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright(c) 2007-2013 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#if 0
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__KERNEL_RCSID(0, "$NetBSD: qat_c2xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
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#endif
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "qatreg.h"
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#include "qat_hw15reg.h"
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#include "qat_c2xxxreg.h"
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#include "qatvar.h"
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#include "qat_hw15var.h"
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static uint32_t
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qat_c2xxx_get_accel_mask(struct qat_softc *sc)
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{
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uint32_t fusectl;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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return ((~fusectl) & ACCEL_MASK_C2XXX);
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}
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static uint32_t
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qat_c2xxx_get_ae_mask(struct qat_softc *sc)
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{
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uint32_t fusectl;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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if (fusectl & (
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FUSECTL_C2XXX_PKE_DISABLE |
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FUSECTL_C2XXX_ATH_DISABLE |
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FUSECTL_C2XXX_CPH_DISABLE)) {
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return 0;
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} else {
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if ((~fusectl & AE_MASK_C2XXX) == 0x3) {
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/*
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* With both AEs enabled we get spurious completions on
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* ETR rings. Work around that for now by simply
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* disabling the second AE.
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*/
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device_printf(sc->sc_dev, "disabling second AE\n");
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fusectl |= 0x2;
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}
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return ((~fusectl) & AE_MASK_C2XXX);
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}
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}
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static enum qat_sku
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qat_c2xxx_get_sku(struct qat_softc *sc)
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{
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uint32_t fusectl;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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switch (sc->sc_ae_num) {
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case 1:
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if (fusectl & FUSECTL_C2XXX_LOW_SKU)
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return QAT_SKU_3;
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else if (fusectl & FUSECTL_C2XXX_MID_SKU)
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return QAT_SKU_2;
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break;
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case MAX_AE_C2XXX:
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return QAT_SKU_1;
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}
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return QAT_SKU_UNKNOWN;
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}
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static uint32_t
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qat_c2xxx_get_accel_cap(struct qat_softc *sc)
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{
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return QAT_ACCEL_CAP_CRYPTO_SYMMETRIC |
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QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC |
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QAT_ACCEL_CAP_CIPHER |
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QAT_ACCEL_CAP_AUTHENTICATION;
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}
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static const char *
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qat_c2xxx_get_fw_uof_name(struct qat_softc *sc)
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{
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if (sc->sc_rev < QAT_REVID_C2XXX_B0)
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return AE_FW_UOF_NAME_C2XXX_A0;
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/* QAT_REVID_C2XXX_B0 and QAT_REVID_C2XXX_C0 */
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return AE_FW_UOF_NAME_C2XXX_B0;
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}
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static void
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qat_c2xxx_enable_intr(struct qat_softc *sc)
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{
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qat_misc_write_4(sc, EP_SMIA_C2XXX, EP_SMIA_MASK_C2XXX);
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}
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static void
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qat_c2xxx_init_etr_intr(struct qat_softc *sc, int bank)
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{
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/*
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* For now, all rings within the bank are setup such that the generation
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* of flag interrupts will be triggered when ring leaves the empty
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* state. Note that in order for the ring interrupt to generate an IRQ
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* the interrupt must also be enabled for the ring.
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*/
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qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL,
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ETR_INT_SRCSEL_MASK_0_C2XXX);
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qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL_2,
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ETR_INT_SRCSEL_MASK_X_C2XXX);
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}
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const struct qat_hw qat_hw_c2xxx = {
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.qhw_sram_bar_id = BAR_SRAM_ID_C2XXX,
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.qhw_misc_bar_id = BAR_PMISC_ID_C2XXX,
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.qhw_etr_bar_id = BAR_ETR_ID_C2XXX,
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.qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C2XXX,
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.qhw_ae_offset = AE_OFFSET_C2XXX,
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.qhw_ae_local_offset = AE_LOCAL_OFFSET_C2XXX,
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.qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C2XXX,
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.qhw_num_banks = ETR_MAX_BANKS_C2XXX,
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.qhw_num_ap_banks = ETR_MAX_AP_BANKS_C2XXX,
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.qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
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.qhw_num_accel = MAX_ACCEL_C2XXX,
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.qhw_num_engines = MAX_AE_C2XXX,
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.qhw_tx_rx_gap = ETR_TX_RX_GAP_C2XXX,
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.qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C2XXX,
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.qhw_msix_ae_vec_gap = MSIX_AE_VEC_GAP_C2XXX,
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.qhw_fw_auth = false,
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.qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW15,
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.qhw_fw_resp_size = FW_REQ_DEFAULT_SZ_HW15,
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.qhw_ring_asym_tx = 2,
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.qhw_ring_asym_rx = 3,
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.qhw_ring_sym_tx = 4,
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.qhw_ring_sym_rx = 5,
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.qhw_mof_fwname = AE_FW_MOF_NAME_C2XXX,
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.qhw_mmp_fwname = AE_FW_MMP_NAME_C2XXX,
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.qhw_prod_type = AE_FW_PROD_TYPE_C2XXX,
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.qhw_get_accel_mask = qat_c2xxx_get_accel_mask,
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.qhw_get_ae_mask = qat_c2xxx_get_ae_mask,
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.qhw_get_sku = qat_c2xxx_get_sku,
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.qhw_get_accel_cap = qat_c2xxx_get_accel_cap,
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.qhw_get_fw_uof_name = qat_c2xxx_get_fw_uof_name,
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.qhw_enable_intr = qat_c2xxx_enable_intr,
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.qhw_init_etr_intr = qat_c2xxx_init_etr_intr,
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.qhw_init_admin_comms = qat_adm_ring_init,
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.qhw_send_admin_init = qat_adm_ring_send_init,
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.qhw_crypto_setup_desc = qat_hw15_crypto_setup_desc,
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.qhw_crypto_setup_req_params = qat_hw15_crypto_setup_req_params,
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.qhw_crypto_opaque_offset =
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offsetof(struct fw_la_resp, comn_resp.opaque_data),
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};
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