mirror of
https://github.com/freebsd/freebsd-src
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71625ec9ad
Remove /^/[*/]\s*\$FreeBSD\$.*\n/
148 lines
3.7 KiB
C
148 lines
3.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright(c) 2021 Intel Corporation */
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#include "adf_gen2_hw_data.h"
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#include "icp_qat_hw.h"
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static u64
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build_csr_ring_base_addr(bus_addr_t addr, u32 size)
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{
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return BUILD_RING_BASE_ADDR(addr, size);
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}
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static u32
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read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring)
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{
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return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
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}
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static void
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write_csr_ring_head(struct resource *csr_base_addr,
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u32 bank,
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u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
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}
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static u32
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read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring)
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{
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return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
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}
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static void
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write_csr_ring_tail(struct resource *csr_base_addr,
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u32 bank,
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u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
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}
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static u32
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read_csr_e_stat(struct resource *csr_base_addr, u32 bank)
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{
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return READ_CSR_E_STAT(csr_base_addr, bank);
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}
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static void
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write_csr_ring_config(struct resource *csr_base_addr,
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u32 bank,
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u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
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}
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static dma_addr_t
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read_csr_ring_base(struct resource *csr_base_addr, u32 bank, u32 ring)
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{
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return READ_CSR_RING_BASE(csr_base_addr, bank, ring);
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}
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static void
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write_csr_ring_base(struct resource *csr_base_addr,
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u32 bank,
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u32 ring,
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bus_addr_t addr)
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{
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WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
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}
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static void
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write_csr_int_flag(struct resource *csr_base_addr, u32 bank, u32 value)
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{
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WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
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}
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static void
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write_csr_int_srcsel(struct resource *csr_base_addr, u32 bank)
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{
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WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
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}
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static void
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write_csr_int_col_en(struct resource *csr_base_addr, u32 bank, u32 value)
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{
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WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
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}
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static void
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write_csr_int_col_ctl(struct resource *csr_base_addr, u32 bank, u32 value)
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{
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WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
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}
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static void
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write_csr_int_flag_and_col(struct resource *csr_base_addr, u32 bank, u32 value)
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{
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WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
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}
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static u32
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read_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank)
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{
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return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank);
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}
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static void
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write_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank, u32 value)
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{
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WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
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}
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static u32
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get_int_col_ctl_enable_mask(void)
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{
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return ADF_RING_CSR_INT_COL_CTL_ENABLE;
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}
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void
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adf_gen2_init_hw_csr_info(struct adf_hw_csr_info *csr_info)
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{
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struct adf_hw_csr_ops *csr_ops = &csr_info->csr_ops;
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csr_info->arb_enable_mask = 0xFF;
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csr_info->csr_addr_offset = ADF_RING_CSR_ADDR_OFFSET;
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csr_info->ring_bundle_size = ADF_RING_BUNDLE_SIZE;
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csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
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csr_ops->read_csr_ring_head = read_csr_ring_head;
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csr_ops->write_csr_ring_head = write_csr_ring_head;
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csr_ops->read_csr_ring_tail = read_csr_ring_tail;
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csr_ops->write_csr_ring_tail = write_csr_ring_tail;
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csr_ops->read_csr_e_stat = read_csr_e_stat;
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csr_ops->write_csr_ring_config = write_csr_ring_config;
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csr_ops->read_csr_ring_base = read_csr_ring_base;
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csr_ops->write_csr_ring_base = write_csr_ring_base;
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csr_ops->write_csr_int_flag = write_csr_int_flag;
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csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
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csr_ops->write_csr_int_col_en = write_csr_int_col_en;
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csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
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csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
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csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en;
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csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
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csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask;
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}
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