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5b5f7d0e77
Update Intel irdma driver to version 1.2.36-k. Notable changes: - Start using ib_sge directly instead of irdma_sge - Turn off flush completion generator for libirdma - Minor formatting changes Signed-off-by: Bartosz Sobczak <bartosz.sobczak@intel.com> Signed-off-by: Eric Joyner <erj@FreeBSD.org> Reviewed by: erj@ MFC after: 3 days Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D43567
234 lines
6.7 KiB
C
234 lines
6.7 KiB
C
/*-
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* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
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*
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* Copyright (c) 2017 - 2022 Intel Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef IRDMA_H
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#define IRDMA_H
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#define RDMA_BIT2(type, a) ((u##type) 1UL << a)
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#define RDMA_MASK3(type, mask, shift) ((u##type) mask << shift)
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#define MAKEMASK(m, s) ((m) << (s))
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#define IRDMA_WQEALLOC_WQE_DESC_INDEX_S 20
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#define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20)
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#define IRDMA_CQPTAIL_WQTAIL_S 0
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#define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0)
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#define IRDMA_CQPTAIL_CQP_OP_ERR_S 31
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#define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31)
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#define IRDMA_CQPERRCODES_CQP_MINOR_CODE_S 0
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#define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0)
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#define IRDMA_CQPERRCODES_CQP_MAJOR_CODE_S 16
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#define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16)
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#define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE_S 4
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#define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4)
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#define IRDMA_GLINT_RATE_INTERVAL_S 0
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#define IRDMA_GLINT_RATE_INTERVAL GENMASK(4, 0)
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#define IRDMA_GLINT_RATE_INTRL_ENA_S 6
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#define IRDMA_GLINT_RATE_INTRL_ENA_M BIT(6)
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#define IRDMA_GLINT_RATE_INTRL_ENA BIT(6)
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#define IRDMA_GLINT_DYN_CTL_INTENA_S 0
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#define IRDMA_GLINT_DYN_CTL_INTENA BIT(0)
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#define IRDMA_GLINT_DYN_CTL_CLEARPBA_S 1
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#define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1)
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#define IRDMA_GLINT_DYN_CTL_ITR_INDX_S 3
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#define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3)
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#define IRDMA_GLINT_DYN_CTL_INTERVAL_S 5
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#define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5)
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#define IRDMA_GLINT_CEQCTL_ITR_INDX_S 11
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#define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11)
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#define IRDMA_GLINT_CEQCTL_CAUSE_ENA_S 30
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#define IRDMA_GLINT_CEQCTL_CAUSE_ENA BIT(30)
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#define IRDMA_GLINT_CEQCTL_MSIX_INDX_S 0
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#define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0)
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#define IRDMA_PFINT_AEQCTL_MSIX_INDX_S 0
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#define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0)
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#define IRDMA_PFINT_AEQCTL_ITR_INDX_S 11
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#define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11)
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#define IRDMA_PFINT_AEQCTL_CAUSE_ENA_S 30
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#define IRDMA_PFINT_AEQCTL_CAUSE_ENA BIT(30)
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#define IRDMA_PFHMC_PDINV_PMSDIDX_S 0
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#define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0)
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#define IRDMA_PFHMC_PDINV_PMSDPARTSEL_S 15
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#define IRDMA_PFHMC_PDINV_PMSDPARTSEL BIT(15)
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#define IRDMA_PFHMC_PDINV_PMPDIDX_S 16
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#define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16)
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#define IRDMA_PFHMC_SDDATALOW_PMSDVALID_S 0
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#define IRDMA_PFHMC_SDDATALOW_PMSDVALID BIT(0)
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#define IRDMA_PFHMC_SDDATALOW_PMSDTYPE_S 1
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#define IRDMA_PFHMC_SDDATALOW_PMSDTYPE BIT(1)
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#define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT_S 2
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#define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2)
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#define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW_S 12
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#define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12)
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#define IRDMA_PFHMC_SDCMD_PMSDWR_S 31
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#define IRDMA_PFHMC_SDCMD_PMSDWR BIT(31)
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#define IRDMA_PFHMC_SDCMD_PMSDPARTSEL_S 15
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#define IRDMA_PFHMC_SDCMD_PMSDPARTSEL BIT(15)
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#define IRDMA_INVALID_CQ_IDX 0xffffffff
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enum irdma_dyn_idx_t {
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IRDMA_IDX_ITR0 = 0,
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IRDMA_IDX_ITR1 = 1,
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IRDMA_IDX_ITR2 = 2,
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IRDMA_IDX_NOITR = 3,
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};
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enum irdma_registers {
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IRDMA_CQPTAIL,
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IRDMA_CQPDB,
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IRDMA_CCQPSTATUS,
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IRDMA_CCQPHIGH,
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IRDMA_CCQPLOW,
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IRDMA_CQARM,
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IRDMA_CQACK,
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IRDMA_AEQALLOC,
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IRDMA_CQPERRCODES,
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IRDMA_WQEALLOC,
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IRDMA_GLINT_DYN_CTL,
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IRDMA_DB_ADDR_OFFSET,
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IRDMA_GLPCI_LBARCTRL,
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IRDMA_GLPE_CPUSTATUS0,
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IRDMA_GLPE_CPUSTATUS1,
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IRDMA_GLPE_CPUSTATUS2,
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IRDMA_PFINT_AEQCTL,
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IRDMA_GLINT_CEQCTL,
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IRDMA_VSIQF_PE_CTL1,
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IRDMA_PFHMC_PDINV,
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IRDMA_GLHMC_VFPDINV,
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IRDMA_GLPE_CRITERR,
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IRDMA_GLINT_RATE,
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IRDMA_MAX_REGS, /* Must be last entry */
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};
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enum irdma_shifts {
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IRDMA_CCQPSTATUS_CCQP_DONE_S,
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IRDMA_CCQPSTATUS_CCQP_ERR_S,
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IRDMA_CQPSQ_STAG_PDID_S,
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IRDMA_CQPSQ_CQ_CEQID_S,
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IRDMA_CQPSQ_CQ_CQID_S,
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IRDMA_COMMIT_FPM_CQCNT_S,
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IRDMA_CQPSQ_UPESD_HMCFNID_S,
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IRDMA_MAX_SHIFTS,
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};
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enum irdma_masks {
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IRDMA_CCQPSTATUS_CCQP_DONE_M,
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IRDMA_CCQPSTATUS_CCQP_ERR_M,
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IRDMA_CQPSQ_STAG_PDID_M,
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IRDMA_CQPSQ_CQ_CEQID_M,
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IRDMA_CQPSQ_CQ_CQID_M,
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IRDMA_COMMIT_FPM_CQCNT_M,
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IRDMA_CQPSQ_UPESD_HMCFNID_M,
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IRDMA_MAX_MASKS, /* Must be last entry */
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};
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#define IRDMA_MAX_MGS_PER_CTX 8
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struct irdma_mcast_grp_ctx_entry_info {
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u32 qp_id;
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bool valid_entry;
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u16 dest_port;
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u32 use_cnt;
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};
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struct irdma_mcast_grp_info {
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u8 dest_mac_addr[ETHER_ADDR_LEN];
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u16 vlan_id;
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u16 hmc_fcn_id;
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bool ipv4_valid:1;
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bool vlan_valid:1;
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u16 mg_id;
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u32 no_of_mgs;
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u32 dest_ip_addr[4];
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u16 qs_handle;
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struct irdma_dma_mem dma_mem_mc;
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struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX];
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};
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enum irdma_vers {
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IRDMA_GEN_RSVD = 0,
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IRDMA_GEN_1 = 1,
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IRDMA_GEN_2 = 2,
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IRDMA_GEN_MAX = IRDMA_GEN_2,
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};
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struct irdma_uk_attrs {
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u64 feature_flags;
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u32 max_hw_wq_frags;
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u32 max_hw_read_sges;
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u32 max_hw_inline;
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u32 max_hw_rq_quanta;
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u32 max_hw_wq_quanta;
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u32 min_hw_cq_size;
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u32 max_hw_cq_size;
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u16 max_hw_sq_chunk;
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u16 min_hw_wq_size;
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u8 hw_rev;
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};
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struct irdma_hw_attrs {
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struct irdma_uk_attrs uk_attrs;
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u64 max_hw_outbound_msg_size;
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u64 max_hw_inbound_msg_size;
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u64 max_mr_size;
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u64 page_size_cap;
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u32 min_hw_qp_id;
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u32 min_hw_aeq_size;
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u32 max_hw_aeq_size;
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u32 min_hw_ceq_size;
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u32 max_hw_ceq_size;
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u32 max_hw_device_pages;
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u32 max_hw_vf_fpm_id;
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u32 first_hw_vf_fpm_id;
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u32 max_hw_ird;
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u32 max_hw_ord;
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u32 max_hw_wqes;
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u32 max_hw_pds;
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u32 max_hw_ena_vf_count;
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u32 max_qp_wr;
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u32 max_pe_ready_count;
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u32 max_done_count;
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u32 max_sleep_count;
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u32 max_cqp_compl_wait_time_ms;
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u16 max_stat_inst;
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u16 max_stat_idx;
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};
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void icrdma_init_hw(struct irdma_sc_dev *dev);
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void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp);
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#endif /* IRDMA_H*/
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