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5b5f7d0e77
Update Intel irdma driver to version 1.2.36-k. Notable changes: - Start using ib_sge directly instead of irdma_sge - Turn off flush completion generator for libirdma - Minor formatting changes Signed-off-by: Bartosz Sobczak <bartosz.sobczak@intel.com> Signed-off-by: Eric Joyner <erj@FreeBSD.org> Reviewed by: erj@ MFC after: 3 days Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D43567
139 lines
5.1 KiB
C
139 lines
5.1 KiB
C
/*-
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* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
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*
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* Copyright (c) 2017 - 2023 Intel Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef ICRDMA_HW_H
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#define ICRDMA_HW_H
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#include "irdma.h"
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#define VFPE_CQPTAIL1 0x0000a000
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#define VFPE_CQPDB1 0x0000bc00
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#define VFPE_CCQPSTATUS1 0x0000b800
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#define VFPE_CCQPHIGH1 0x00009800
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#define VFPE_CCQPLOW1 0x0000ac00
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#define VFPE_CQARM1 0x0000b400
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#define VFPE_CQARM1 0x0000b400
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#define VFPE_CQACK1 0x0000b000
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#define VFPE_AEQALLOC1 0x0000a400
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#define VFPE_CQPERRCODES1 0x00009c00
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#define VFPE_WQEALLOC1 0x0000c000
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#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */
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#define PFPE_CQPTAIL 0x00500880
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#define PFPE_CQPDB 0x00500800
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#define PFPE_CCQPSTATUS 0x0050a000
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#define PFPE_CCQPHIGH 0x0050a100
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#define PFPE_CCQPLOW 0x0050a080
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#define PFPE_CQARM 0x00502c00
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#define PFPE_CQACK 0x00502c80
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#define PFPE_AEQALLOC 0x00502d00
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#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */
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#define GLPCI_LBARCTRL 0x0009de74
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#define GLPE_CPUSTATUS0 0x0050ba5c
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#define GLPE_CPUSTATUS1 0x0050ba60
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#define GLPE_CPUSTATUS2 0x0050ba64
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#define PFINT_AEQCTL 0x0016cb00
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#define PFPE_CQPERRCODES 0x0050a200
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#define PFPE_WQEALLOC 0x00504400
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#define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */
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#define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */
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#define PFHMC_PDINV 0x00520300
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#define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */
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#define GLPE_CRITERR 0x00534000
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#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
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#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_0 0x001e3180
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#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_1 0x001e3184
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#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_2 0x001e3188
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#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_3 0x001e318c
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#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_0 0x001e31a0
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#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_1 0x001e31a4
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#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_2 0x001e31a8
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#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_3 0x001e31aC
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#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_0 0x001e34c0
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#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_1 0x001e34c4
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#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_2 0x001e34c8
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#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_3 0x001e34cC
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#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_0 0x001e35c0
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#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_1 0x001e35c4
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#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_2 0x001e35c8
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#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_3 0x001e35cC
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#define GLDCB_TC2PFC 0x001d2694
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#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001e31c0
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#define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024)
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#define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024)
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#define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0
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#define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
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#define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31
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#define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
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#define ICRDMA_CQPSQ_STAG_PDID_S 46
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#define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
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#define ICRDMA_CQPSQ_CQ_CEQID_S 22
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#define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
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#define ICRDMA_CQPSQ_CQ_CQID_S 0
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#define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
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#define ICRDMA_COMMIT_FPM_CQCNT_S 0
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#define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
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#define ICRDMA_CQPSQ_UPESD_HMCFNID_S 0
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#define ICRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
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enum icrdma_device_caps_const {
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ICRDMA_MAX_WQ_FRAGMENT_COUNT = 13,
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ICRDMA_MAX_SGE_RD = 13,
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ICRDMA_MAX_STATS_COUNT = 128,
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ICRDMA_MAX_IRD_SIZE = 32,
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ICRDMA_MAX_ORD_SIZE = 32,
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ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */,
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ICRDMA_MAX_PUSH_PAGE_COUNT = 256,
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};
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void icrdma_init_hw(struct irdma_sc_dev *dev);
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void irdma_init_config_check(struct irdma_config_check *cc,
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u8 traffic_class,
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u16 qs_handle);
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bool irdma_is_config_ok(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi);
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void irdma_check_fc_for_tc_update(struct irdma_sc_vsi *vsi,
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struct irdma_l2params *l2params);
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void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp);
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#endif /* ICRDMA_HW_H*/
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