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91 lines
2.6 KiB
C
91 lines
2.6 KiB
C
/*-
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* Copyright (C) 2012 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __IOAT_TEST_H__
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#define __IOAT_TEST_H__
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enum ioat_res {
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IOAT_TEST_OK = 0,
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IOAT_TEST_NO_DMA_ENGINE,
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IOAT_TEST_NO_MEMORY,
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IOAT_TEST_MISCOMPARE,
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IOAT_TEST_INVALID_INPUT,
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IOAT_NUM_RES
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};
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enum ioat_test_kind {
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IOAT_TEST_FILL = 0,
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IOAT_TEST_DMA,
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IOAT_TEST_RAW_DMA,
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IOAT_TEST_DMA_8K,
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IOAT_TEST_MEMCPY,
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IOAT_TEST_DMA_8K_PB,
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IOAT_TEST_DMA_CRC,
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IOAT_TEST_DMA_CRC_COPY,
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IOAT_NUM_TESTKINDS
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};
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struct test_transaction;
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struct ioat_test {
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volatile uint32_t status[IOAT_NUM_RES];
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uint32_t channel_index;
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enum ioat_test_kind testkind;
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/* HW max of 1MB */
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uint32_t buffer_size;
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uint32_t chain_depth;
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uint32_t transactions;
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/*
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* If non-zero, duration is time in ms;
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* If zero, bounded by 'transactions' above.
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*/
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uint32_t duration;
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/* If true, check for miscompares after a copy. */
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bool verify;
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/* DMA directly to/from some memory address */
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uint64_t raw_target;
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void *raw_vtarget;
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bool raw_write;
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bool raw_is_virtual;
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bool zero_stats;
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/* Configure coalesce period */
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uint16_t coalesce_period;
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/* Internal usage -- not test inputs */
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TAILQ_HEAD(, test_transaction) free_q;
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TAILQ_HEAD(, test_transaction) pend_q;
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volatile bool too_late;
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};
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#define IOAT_DMATEST _IOWR('i', 0, struct ioat_test)
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#endif /* __IOAT_TEST_H__ */
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