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251 lines
9.2 KiB
C
251 lines
9.2 KiB
C
/*-
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* Copyright (C) 2012 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __IOAT_H__
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#define __IOAT_H__
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#include <sys/param.h>
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#include <machine/bus.h>
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/*
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* This file defines the public interface to the IOAT driver.
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*/
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/*
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* Enables an interrupt for this operation. Typically, you would only enable
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* this on the last operation in a group
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*/
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#define DMA_INT_EN 0x1
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/*
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* Like M_NOWAIT. Operations will return NULL if they cannot allocate a
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* descriptor without blocking.
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*/
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#define DMA_NO_WAIT 0x2
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/*
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* Disallow prefetching the source of the following operation. Ordinarily, DMA
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* operations can be pipelined on some hardware. E.g., operation 2's source
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* may be prefetched before operation 1 completes.
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*/
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#define DMA_FENCE 0x4
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#define _DMA_GENERIC_FLAGS (DMA_INT_EN | DMA_NO_WAIT | DMA_FENCE)
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/*
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* Emit a CRC32C as the result of a ioat_copy_crc() or ioat_crc().
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*/
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#define DMA_CRC_STORE 0x8
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/*
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* Compare the CRC32C of a ioat_copy_crc() or ioat_crc() against an expeceted
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* value. It is invalid to specify both TEST and STORE.
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*/
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#define DMA_CRC_TEST 0x10
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#define _DMA_CRC_TESTSTORE (DMA_CRC_STORE | DMA_CRC_TEST)
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/*
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* Use an inline comparison CRC32C or emit an inline CRC32C result. Invalid
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* without one of STORE or TEST.
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*/
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#define DMA_CRC_INLINE 0x20
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#define _DMA_CRC_FLAGS (DMA_CRC_STORE | DMA_CRC_TEST | DMA_CRC_INLINE)
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/*
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* Hardware revision number. Different hardware revisions support different
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* features. For example, 3.2 cannot read from MMIO space, while 3.3 can.
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*/
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#define IOAT_VER_3_0 0x30
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#define IOAT_VER_3_2 0x32
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#define IOAT_VER_3_3 0x33
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/*
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* Hardware capabilities. Different hardware revisions support different
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* features. It is often useful to detect specific features than try to infer
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* them from hardware version.
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*
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* Different channels may support different features too; for example, 'PQ' may
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* only be supported on the first two channels of some hardware.
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*/
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#define IOAT_DMACAP_PB (1 << 0)
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#define IOAT_DMACAP_CRC (1 << 1)
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#define IOAT_DMACAP_MARKER_SKIP (1 << 2)
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#define IOAT_DMACAP_OLD_XOR (1 << 3)
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#define IOAT_DMACAP_DCA (1 << 4)
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#define IOAT_DMACAP_MOVECRC (1 << 5)
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#define IOAT_DMACAP_BFILL (1 << 6)
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#define IOAT_DMACAP_EXT_APIC (1 << 7)
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#define IOAT_DMACAP_XOR (1 << 8)
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#define IOAT_DMACAP_PQ (1 << 9)
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#define IOAT_DMACAP_DMA_DIF (1 << 10)
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#define IOAT_DMACAP_DWBES (1 << 13)
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#define IOAT_DMACAP_RAID16SS (1 << 17)
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#define IOAT_DMACAP_DMAMC (1 << 18)
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#define IOAT_DMACAP_CTOS (1 << 19)
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#define IOAT_DMACAP_STR \
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"\20\24Completion_Timeout_Support\23DMA_with_Multicasting_Support" \
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"\22RAID_Super_descriptors\16Descriptor_Write_Back_Error_Support" \
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"\13DMA_with_DIF\12PQ\11XOR\10Extended_APIC_ID\07Block_Fill\06Move_CRC" \
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"\05DCA\04Old_XOR\03Marker_Skipping\02CRC\01Page_Break"
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typedef void *bus_dmaengine_t;
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struct bus_dmadesc;
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typedef void (*bus_dmaengine_callback_t)(void *arg, int error);
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unsigned ioat_get_nchannels(void);
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/*
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* Called first to acquire a reference to the DMA channel
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*
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* Flags may be M_WAITOK or M_NOWAIT.
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*/
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bus_dmaengine_t ioat_get_dmaengine(uint32_t channel_index, int flags);
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/* Release the DMA channel */
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void ioat_put_dmaengine(bus_dmaengine_t dmaengine);
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/* Check the DMA engine's HW version */
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int ioat_get_hwversion(bus_dmaengine_t dmaengine);
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size_t ioat_get_max_io_size(bus_dmaengine_t dmaengine);
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uint32_t ioat_get_capabilities(bus_dmaengine_t dmaengine);
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int ioat_get_domain(bus_dmaengine_t dmaengine, int *domain);
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/*
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* Set interrupt coalescing on a DMA channel.
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*
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* The argument is in microseconds. A zero value disables coalescing. Any
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* other value delays interrupt generation for N microseconds to provide
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* opportunity to coalesce multiple operations into a single interrupt.
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*
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* Returns an error status, or zero on success.
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*
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* - ERANGE if the given value exceeds the delay supported by the hardware.
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* (All current hardware supports a maximum of 0x3fff microseconds delay.)
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* - ENODEV if the hardware does not support interrupt coalescing.
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*/
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int ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay);
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/*
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* Return the maximum supported coalescing period, for use in
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* ioat_set_interrupt_coalesce(). If the hardware does not support coalescing,
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* returns zero.
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*/
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uint16_t ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine);
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/*
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* Acquire must be called before issuing an operation to perform. Release is
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* called after. Multiple operations can be issued within the context of one
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* acquire and release
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*/
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void ioat_acquire(bus_dmaengine_t dmaengine);
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void ioat_release(bus_dmaengine_t dmaengine);
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/*
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* Acquire_reserve can be called to ensure there is room for N descriptors. If
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* it succeeds, the next N valid operations will successfully enqueue.
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*
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* It may fail with:
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* - ENXIO if the channel is in an errored state, or the driver is being
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* unloaded
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* - EAGAIN if mflags included M_NOWAIT
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*
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* On failure, the caller does not hold the dmaengine.
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*/
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int ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags)
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__result_use_check;
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/*
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* Issue a blockfill operation. The 64-bit pattern 'fillpattern' is written to
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* 'len' physically contiguous bytes at 'dst'.
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*
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* Only supported on devices with the BFILL capability.
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*/
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struct bus_dmadesc *ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst,
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uint64_t fillpattern, bus_size_t len, bus_dmaengine_callback_t callback_fn,
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void *callback_arg, uint32_t flags);
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/* Issues the copy data operation */
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struct bus_dmadesc *ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
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bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
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void *callback_arg, uint32_t flags);
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/*
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* Issue a copy data operation, with constraints:
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* - src1, src2, dst1, dst2 are all page-aligned addresses
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* - The quantity to copy is exactly 2 pages;
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* - src1 -> dst1, src2 -> dst2
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*
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* Why use this instead of normal _copy()? You can copy two non-contiguous
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* pages (src, dst, or both) with one descriptor.
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*/
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struct bus_dmadesc *ioat_copy_8k_aligned(bus_dmaengine_t dmaengine,
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bus_addr_t dst1, bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
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/*
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* Copy len bytes from dst to src, like ioat_copy().
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*
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* Additionally, accumulate a CRC32C of the data.
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*
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* If initialseed is not NULL, the value it points to is used to seed the
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* initial value of the CRC32C.
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*
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* If flags include DMA_CRC_STORE and not DMA_CRC_INLINE, crcptr is written
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* with the 32-bit CRC32C result (in wire format).
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*
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* If flags include DMA_CRC_TEST and not DMA_CRC_INLINE, the computed CRC32C is
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* compared with the 32-bit CRC32C pointed to by crcptr. If they do not match,
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* a channel error is raised.
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*
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* If the DMA_CRC_INLINE flag is set, crcptr is ignored and the DMA engine uses
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* the 4 bytes trailing the source data (TEST) or the destination data (STORE).
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*/
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struct bus_dmadesc *ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst,
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bus_addr_t src, bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
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/*
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* ioat_crc() is nearly identical to ioat_copy_crc(), but does not actually
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* move data around.
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*
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* Like ioat_copy_crc, ioat_crc computes a CRC32C over len bytes pointed to by
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* src. The flags affect its operation in the same way, with one exception:
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*
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* If flags includes both DMA_CRC_STORE and DMA_CRC_INLINE, the computed CRC32C
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* is written to the 4 bytes trailing the *source* data.
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*/
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struct bus_dmadesc *ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src,
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bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
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/*
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* Issues a null operation. This issues the operation to the hardware, but the
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* hardware doesn't do anything with it.
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*/
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struct bus_dmadesc *ioat_null(bus_dmaengine_t dmaengine,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
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#endif /* __IOAT_H__ */
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