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84 lines
3 KiB
C
84 lines
3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
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*
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* Copyright (c) 2017-2018 Panasas
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DEV__IMCSMB__IMCSMB_REG_H_
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#define _DEV__IMCSMB__IMCSMB_REG_H_
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/endian.h>
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#include <sys/errno.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/syslog.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/atomic.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/smbus/smbconf.h>
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/* Intel (Sandy,Ivy)bridge and (Has,Broad)well CPUs have integrated memory
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* controllers (iMCs), each of which having up to two SMBus controllers. They
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* are programmed via sets of registers in the same PCI device, which are
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* identical other than the register numbers.
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*
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* The full documentation for these registers can be found in volume two of the
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* datasheets for the CPUs. Refer to the links in imcsmb_pci.c
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*/
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#define IMCSMB_REG_STATUS0 0x0180
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#define IMCSMB_REG_STATUS1 0x0190
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#define IMCSMB_STATUS_BUSY_BIT 0x10000000
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#define IMCSMB_STATUS_BUS_ERROR_BIT 0x20000000
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#define IMCSMB_STATUS_WRITE_DATA_DONE 0x40000000
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#define IMCSMB_STATUS_READ_DATA_VALID 0x80000000
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#define IMCSMB_REG_COMMAND0 0x0184
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#define IMCSMB_REG_COMMAND1 0x0194
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#define IMCSMB_CMD_WORD_ACCESS 0x20000000
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#define IMCSMB_CMD_WRITE_BIT 0x08000000
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#define IMCSMB_CMD_TRIGGER_BIT 0x80000000
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#define IMCSMB_REG_CONTROL0 0x0188
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#define IMCSMB_REG_CONTROL1 0x0198
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#define IMCSMB_CNTL_POLL_EN 0x00000100
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#define IMCSMB_CNTL_CLK_OVERRIDE 0x08000000
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#define IMCSMB_CNTL_DTI_MASK 0xf0000000
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#define IMCSMB_CNTL_WRITE_DISABLE_BIT 0x04000000
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#endif /* _DEV__IMCSMB__IMCSMB_REG_H_ */
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/* vi: set ts=8 sw=4 sts=8 noet: */
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