mirror of
https://github.com/freebsd/freebsd-src
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547 lines
12 KiB
C
547 lines
12 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _IGC_HW_H_
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#define _IGC_HW_H_
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#include "igc_osdep.h"
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#include "igc_regs.h"
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#include "igc_defines.h"
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struct igc_hw;
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#define IGC_DEV_ID_I225_LM 0x15F2
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#define IGC_DEV_ID_I225_V 0x15F3
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#define IGC_DEV_ID_I225_K 0x3100
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#define IGC_DEV_ID_I225_I 0x15F8
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#define IGC_DEV_ID_I220_V 0x15F7
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#define IGC_DEV_ID_I225_K2 0x3101
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#define IGC_DEV_ID_I225_LMVP 0x5502
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#define IGC_DEV_ID_I226_K 0x3102
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#define IGC_DEV_ID_I226_LMVP 0x5503
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#define IGC_DEV_ID_I225_IT 0x0D9F
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#define IGC_DEV_ID_I226_LM 0x125B
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#define IGC_DEV_ID_I226_V 0x125C
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#define IGC_DEV_ID_I226_IT 0x125D
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#define IGC_DEV_ID_I221_V 0x125E
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#define IGC_DEV_ID_I226_BLANK_NVM 0x125F
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#define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
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#define IGC_REVISION_0 0
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#define IGC_REVISION_1 1
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#define IGC_REVISION_2 2
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#define IGC_REVISION_3 3
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#define IGC_REVISION_4 4
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#define IGC_FUNC_1 1
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#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
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#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
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enum igc_mac_type {
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igc_undefined = 0,
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igc_i225,
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igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
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};
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enum igc_media_type {
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igc_media_type_unknown = 0,
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igc_media_type_copper = 1,
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igc_num_media_types
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};
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enum igc_nvm_type {
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igc_nvm_unknown = 0,
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igc_nvm_eeprom_spi,
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igc_nvm_flash_hw,
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igc_nvm_invm,
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};
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enum igc_phy_type {
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igc_phy_unknown = 0,
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igc_phy_none,
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igc_phy_i225,
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};
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enum igc_bus_type {
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igc_bus_type_unknown = 0,
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igc_bus_type_pci,
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igc_bus_type_pcix,
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igc_bus_type_pci_express,
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igc_bus_type_reserved
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};
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enum igc_bus_speed {
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igc_bus_speed_unknown = 0,
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igc_bus_speed_33,
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igc_bus_speed_66,
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igc_bus_speed_100,
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igc_bus_speed_120,
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igc_bus_speed_133,
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igc_bus_speed_2500,
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igc_bus_speed_5000,
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igc_bus_speed_reserved
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};
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enum igc_bus_width {
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igc_bus_width_unknown = 0,
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igc_bus_width_pcie_x1,
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igc_bus_width_pcie_x2,
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igc_bus_width_pcie_x4 = 4,
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igc_bus_width_pcie_x8 = 8,
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igc_bus_width_32,
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igc_bus_width_64,
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igc_bus_width_reserved
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};
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enum igc_fc_mode {
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igc_fc_none = 0,
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igc_fc_rx_pause,
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igc_fc_tx_pause,
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igc_fc_full,
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igc_fc_default = 0xFF
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};
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enum igc_ms_type {
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igc_ms_hw_default = 0,
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igc_ms_force_master,
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igc_ms_force_slave,
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igc_ms_auto
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};
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enum igc_smart_speed {
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igc_smart_speed_default = 0,
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igc_smart_speed_on,
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igc_smart_speed_off
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};
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#define __le16 u16
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#define __le32 u32
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#define __le64 u64
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/* Receive Descriptor */
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struct igc_rx_desc {
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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__le16 length; /* Length of data DMAed into data buffer */
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__le16 csum; /* Packet checksum */
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u8 status; /* Descriptor status */
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u8 errors; /* Descriptor Errors */
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__le16 special;
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};
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/* Receive Descriptor - Extended */
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union igc_rx_desc_extended {
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struct {
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__le64 buffer_addr;
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__le64 reserved;
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} read;
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struct {
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struct {
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__le32 mrq; /* Multiple Rx Queues */
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union {
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__le32 rss; /* RSS Hash */
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struct {
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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__le32 status_error; /* ext status/error */
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__le16 length;
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__le16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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#define MAX_PS_BUFFERS 4
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/* Number of packet split data buffers (not including the header buffer) */
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#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
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/* Receive Descriptor - Packet Split */
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union igc_rx_desc_packet_split {
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struct {
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/* one buffer for protocol header(s), three data buffers */
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__le64 buffer_addr[MAX_PS_BUFFERS];
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} read;
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struct {
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struct {
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__le32 mrq; /* Multiple Rx Queues */
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union {
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__le32 rss; /* RSS Hash */
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struct {
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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__le32 status_error; /* ext status/error */
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__le16 length0; /* length of buffer 0 */
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__le16 vlan; /* VLAN tag */
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} middle;
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struct {
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__le16 header_status;
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/* length of buffers 1-3 */
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__le16 length[PS_PAGE_BUFFERS];
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} upper;
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__le64 reserved;
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} wb; /* writeback */
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};
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/* Transmit Descriptor */
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struct igc_tx_desc {
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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union {
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__le32 data;
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struct {
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__le16 length; /* Data buffer length */
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u8 cso; /* Checksum offset */
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u8 cmd; /* Descriptor control */
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} flags;
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} lower;
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union {
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__le32 data;
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struct {
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u8 status; /* Descriptor status */
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u8 css; /* Checksum start */
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__le16 special;
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} fields;
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} upper;
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};
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/* Offload Context Descriptor */
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struct igc_context_desc {
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union {
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__le32 ip_config;
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struct {
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u8 ipcss; /* IP checksum start */
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u8 ipcso; /* IP checksum offset */
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__le16 ipcse; /* IP checksum end */
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} ip_fields;
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} lower_setup;
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union {
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__le32 tcp_config;
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struct {
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u8 tucss; /* TCP checksum start */
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u8 tucso; /* TCP checksum offset */
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__le16 tucse; /* TCP checksum end */
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} tcp_fields;
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} upper_setup;
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__le32 cmd_and_length;
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union {
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__le32 data;
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struct {
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u8 status; /* Descriptor status */
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u8 hdr_len; /* Header length */
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__le16 mss; /* Maximum segment size */
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} fields;
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} tcp_seg_setup;
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};
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/* Offload data descriptor */
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struct igc_data_desc {
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__le64 buffer_addr; /* Address of the descriptor's buffer address */
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union {
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__le32 data;
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struct {
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__le16 length; /* Data buffer length */
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u8 typ_len_ext;
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u8 cmd;
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} flags;
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} lower;
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union {
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__le32 data;
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struct {
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u8 status; /* Descriptor status */
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u8 popts; /* Packet Options */
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__le16 special;
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} fields;
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} upper;
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};
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/* Statistics counters collected by the MAC */
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struct igc_hw_stats {
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u64 crcerrs;
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u64 algnerrc;
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u64 symerrs;
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u64 rxerrc;
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u64 mpc;
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u64 scc;
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u64 ecol;
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u64 mcc;
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u64 latecol;
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u64 colc;
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u64 dc;
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u64 tncrs;
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u64 sec;
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u64 rlec;
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u64 xonrxc;
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u64 xontxc;
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u64 xoffrxc;
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u64 xofftxc;
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u64 fcruc;
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u64 prc64;
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u64 prc127;
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u64 prc255;
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u64 prc511;
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u64 prc1023;
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u64 prc1522;
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u64 tlpic;
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u64 rlpic;
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u64 gprc;
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u64 bprc;
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u64 mprc;
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u64 gptc;
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u64 gorc;
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u64 gotc;
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u64 rnbc;
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u64 ruc;
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u64 rfc;
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u64 roc;
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u64 rjc;
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u64 mgprc;
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u64 mgpdc;
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u64 mgptc;
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u64 tor;
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u64 tot;
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u64 tpr;
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u64 tpt;
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u64 ptc64;
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u64 ptc127;
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u64 ptc255;
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u64 ptc511;
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u64 ptc1023;
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u64 ptc1522;
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u64 mptc;
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u64 bptc;
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u64 tsctc;
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u64 iac;
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u64 rxdmtc;
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u64 htdpmc;
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u64 rpthc;
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u64 hgptc;
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u64 hgorc;
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u64 hgotc;
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u64 lenerrs;
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u64 scvpc;
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u64 hrmpc;
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u64 doosync;
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u64 o2bgptc;
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u64 o2bspc;
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u64 b2ospc;
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u64 b2ogprc;
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};
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#include "igc_mac.h"
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#include "igc_phy.h"
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#include "igc_nvm.h"
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/* Function pointers for the MAC. */
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struct igc_mac_operations {
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s32 (*init_params)(struct igc_hw *);
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s32 (*check_for_link)(struct igc_hw *);
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void (*clear_hw_cntrs)(struct igc_hw *);
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void (*clear_vfta)(struct igc_hw *);
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s32 (*get_bus_info)(struct igc_hw *);
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void (*set_lan_id)(struct igc_hw *);
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s32 (*get_link_up_info)(struct igc_hw *, u16 *, u16 *);
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void (*update_mc_addr_list)(struct igc_hw *, u8 *, u32);
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s32 (*reset_hw)(struct igc_hw *);
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s32 (*init_hw)(struct igc_hw *);
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s32 (*setup_link)(struct igc_hw *);
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s32 (*setup_physical_interface)(struct igc_hw *);
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void (*write_vfta)(struct igc_hw *, u32, u32);
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void (*config_collision_dist)(struct igc_hw *);
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int (*rar_set)(struct igc_hw *, u8*, u32);
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s32 (*read_mac_addr)(struct igc_hw *);
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s32 (*validate_mdi_setting)(struct igc_hw *);
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s32 (*acquire_swfw_sync)(struct igc_hw *, u16);
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void (*release_swfw_sync)(struct igc_hw *, u16);
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};
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/* When to use various PHY register access functions:
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*
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* Func Caller
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* Function Does Does When to use
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* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* X_reg L,P,A n/a for simple PHY reg accesses
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* X_reg_locked P,A L for multiple accesses of different regs
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* on different pages
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* X_reg_page A L,P for multiple accesses of different regs
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* on the same page
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*
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* Where X=[read|write], L=locking, P=sets page, A=register access
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*
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*/
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struct igc_phy_operations {
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s32 (*init_params)(struct igc_hw *);
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s32 (*acquire)(struct igc_hw *);
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s32 (*check_reset_block)(struct igc_hw *);
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s32 (*force_speed_duplex)(struct igc_hw *);
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s32 (*get_info)(struct igc_hw *);
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s32 (*set_page)(struct igc_hw *, u16);
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s32 (*read_reg)(struct igc_hw *, u32, u16 *);
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s32 (*read_reg_locked)(struct igc_hw *, u32, u16 *);
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s32 (*read_reg_page)(struct igc_hw *, u32, u16 *);
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void (*release)(struct igc_hw *);
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s32 (*reset)(struct igc_hw *);
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s32 (*set_d0_lplu_state)(struct igc_hw *, bool);
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s32 (*set_d3_lplu_state)(struct igc_hw *, bool);
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s32 (*write_reg)(struct igc_hw *, u32, u16);
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s32 (*write_reg_locked)(struct igc_hw *, u32, u16);
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s32 (*write_reg_page)(struct igc_hw *, u32, u16);
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void (*power_up)(struct igc_hw *);
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void (*power_down)(struct igc_hw *);
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};
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/* Function pointers for the NVM. */
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struct igc_nvm_operations {
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s32 (*init_params)(struct igc_hw *);
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s32 (*acquire)(struct igc_hw *);
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s32 (*read)(struct igc_hw *, u16, u16, u16 *);
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void (*release)(struct igc_hw *);
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void (*reload)(struct igc_hw *);
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s32 (*update)(struct igc_hw *);
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s32 (*validate)(struct igc_hw *);
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s32 (*write)(struct igc_hw *, u16, u16, u16 *);
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};
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struct igc_info {
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s32 (*get_invariants)(struct igc_hw *hw);
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struct igc_mac_operations *mac_ops;
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const struct igc_phy_operations *phy_ops;
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struct igc_nvm_operations *nvm_ops;
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};
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extern const struct igc_info igc_i225_info;
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struct igc_mac_info {
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struct igc_mac_operations ops;
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u8 addr[ETH_ADDR_LEN];
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u8 perm_addr[ETH_ADDR_LEN];
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enum igc_mac_type type;
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u32 mc_filter_type;
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u16 current_ifs_val;
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u16 ifs_max_val;
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u16 ifs_min_val;
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u16 ifs_ratio;
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u16 ifs_step_size;
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u16 mta_reg_count;
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u16 uta_reg_count;
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/* Maximum size of the MTA register table in all supported adapters */
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#define MAX_MTA_REG 128
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u32 mta_shadow[MAX_MTA_REG];
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u16 rar_entry_count;
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u8 forced_speed_duplex;
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bool asf_firmware_present;
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bool autoneg;
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bool get_link_status;
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u32 max_frame_size;
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};
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struct igc_phy_info {
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struct igc_phy_operations ops;
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enum igc_phy_type type;
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enum igc_smart_speed smart_speed;
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u32 addr;
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u32 id;
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u32 reset_delay_us; /* in usec */
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u32 revision;
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enum igc_media_type media_type;
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u16 autoneg_advertised;
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u16 autoneg_mask;
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u8 mdix;
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bool polarity_correction;
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bool speed_downgraded;
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bool autoneg_wait_to_complete;
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};
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struct igc_nvm_info {
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struct igc_nvm_operations ops;
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enum igc_nvm_type type;
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u16 word_size;
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u16 delay_usec;
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u16 address_bits;
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u16 opcode_bits;
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u16 page_size;
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};
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struct igc_bus_info {
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enum igc_bus_type type;
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enum igc_bus_speed speed;
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enum igc_bus_width width;
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u16 func;
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u16 pci_cmd_word;
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};
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struct igc_fc_info {
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u32 high_water; /* Flow control high-water mark */
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u32 low_water; /* Flow control low-water mark */
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u16 pause_time; /* Flow control pause timer */
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u16 refresh_time; /* Flow control refresh timer */
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bool send_xon; /* Flow control send XON */
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bool strict_ieee; /* Strict IEEE mode */
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enum igc_fc_mode current_mode; /* FC mode in effect */
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enum igc_fc_mode requested_mode; /* FC mode requested by caller */
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};
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struct igc_dev_spec_i225 {
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bool eee_disable;
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bool clear_semaphore_once;
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u32 mtu;
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};
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struct igc_hw {
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void *back;
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u8 *hw_addr;
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u8 *flash_address;
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unsigned long io_base;
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struct igc_mac_info mac;
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struct igc_fc_info fc;
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struct igc_phy_info phy;
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struct igc_nvm_info nvm;
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struct igc_bus_info bus;
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union {
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struct igc_dev_spec_i225 _i225;
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} dev_spec;
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u16 device_id;
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u16 subsystem_vendor_id;
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u16 subsystem_device_id;
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u16 vendor_id;
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u8 revision_id;
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};
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#include "igc_i225.h"
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#include "igc_base.h"
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/* These functions must be implemented by drivers */
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s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
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s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
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void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
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void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
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#endif
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