mirror of
https://github.com/freebsd/freebsd-src
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bf2fd47550
Reviewed by: imp, markj, Elliott Mitchell Pull Request: https://github.com/freebsd/freebsd-src/pull/1125
658 lines
25 KiB
C
658 lines
25 KiB
C
/*
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* Copyright (c) 2014 The DragonFly Project. All rights reserved.
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*
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* This code is derived from software contributed to The DragonFly Project
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* by Matthew Dillon <dillon@backplane.com> and was subsequently ported
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* to FreeBSD by Michael Gmelin <freebsd@grem.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of The DragonFly Project nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific, prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Intel fourth generation mobile cpus integrated I2C device.
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*
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* Datasheet reference: Section 22.
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*
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* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf
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*
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* This is a from-scratch driver under the BSD license using the Intel data
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* sheet and the linux driver for reference. All code is freshly written
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* without referencing the linux driver code. However, during testing
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* I am also using the linux driver code as a reference to help resolve any
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* issues that come. These will be specifically documented in the code.
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*
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* This controller is an I2C master only and cannot act as a slave. The IO
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* voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s)
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* and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT
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* supported.
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*/
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#ifndef _ICHIIC_IG4_REG_H_
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#define _ICHIIC_IG4_REG_H_
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/*
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* 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through
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* BAR1 when in ACPI mode.
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*
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* Register width is 32-bits
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*
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* 22.2 Default Values on device reset are 0 except as specified here:
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* TAR_ADD 0x00000055
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* SS_SCL_HCNT 0x00000264
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* SS_SCL_LCNT 0x000002C2
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* FS_SCL_HCNT 0x0000006E
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* FS_SCL_LCNT 0x000000CF
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* INTR_MASK 0x000008FF
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* I2C_STA 0x00000006
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* SDA_HOLD 0x00000001
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* SDA_SETUP 0x00000064
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* COMP_PARAM1 0x00FFFF6E
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*/
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#define IG4_REG_CTL 0x0000 /* RW Control Register */
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#define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */
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#define IG4_REG_HS_MADDR 0x000C /* RW High Speed Master Mode Code Address*/
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#define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */
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#define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */
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#define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */
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#define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */
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#define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */
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#define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */
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#define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */
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#define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */
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#define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */
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#define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */
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#define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */
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#define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */
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#define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */
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#define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */
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#define IG4_REG_CLR_RD_REQ 0x0050 /* RO Clear RD_Req Interrupt */
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#define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */
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#define IG4_REG_CLR_RX_DONE 0x0058 /* RO Clear RX_Done Interrupt */
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#define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */
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#define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */
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#define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */
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#define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */
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#define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */
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#define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */
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#define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */
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#define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */
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#define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */
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#define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */
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#define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */
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#define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */
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#define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */
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#define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */
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#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */
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#define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */
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#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */
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/* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */
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#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */
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#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */
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/* Available at least on Atom SoCs */
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#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */
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/* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */
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#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */
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#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */
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#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */
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#define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */
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#define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */
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#define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */
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/* Available at least on Atom SoCs */
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#define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */
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/* Available at least on Atom SoCs and Haswell mobile */
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#define IG4_REG_RESETS_HSW 0x0804 /* RW Reset Register */
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#define IG4_REG_GENERAL 0x0808 /* RW General Register */
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/* These LTR config registers are at least available on Haswell mobile. */
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#define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */
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#define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */
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/*
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* CTL - Control Register 22.2.1
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* Default Value: 0x0000007F.
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*
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* RESTARTEN - RW Restart Enable
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* 10BIT - RW Controller operates in 10-bit mode, else 7-bit
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*
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* NOTE: When restart is disabled the controller is incapable of
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* performing the following functions:
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*
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* Sending a START Byte
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* Performing any high-speed mode op
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* Performing direction changes in combined format mode
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* Performing a read operation with a 10-bit address
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*
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* Attempting to perform the above operations will result in the
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* TX_ABORT bit being set in RAW_INTR_STAT.
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*/
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#define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */
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#define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */
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#define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */
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#define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */
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#define IG4_CTL_MASTER 0x0001 /* snarfed from linux */
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#define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */
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#define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */
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#define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */
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/*
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* TAR_ADD - Target Address Register 22.2.2
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* Default Value: 0x00000055F
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*
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* 10BIT - RW controller starts its transfers in 10-bit
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* address mode, else 7-bit.
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*
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* SPECIAL - RW Indicates whether software performs a General Call
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* or START BYTE command.
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*
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* 0 Ignore GC_OR_START and use TAR address.
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*
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* 1 Perform special I2C Command based on GC_OR_START.
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*
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* GC_OR_START - RW (only if SPECIAL is set)
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*
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* 0 General Call Address. After issuing a General Call,
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* only writes may be performed. Attempting to issue
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* a read command results in IX_ABRT in RAW_INTR_STAT.
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* The controller remains in General Call mode until
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* bit 11 (SPECIAL) is cleared.
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*
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* 1 START BYTE.
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*
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*
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* IC_TAR - RW when transmitting a general call, these bits are
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* ignored. To generate a START BYTE, the address
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* needs to be written into these bits once.
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*
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* This register should only be updated when the IIC is disabled (I2C_ENABLE=0)
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*/
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#define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */
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#define IG4_TAR_SPECIAL 0x0800 /* Perform special command */
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#define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */
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#define IG4_TAR_ADDR_MASK 0x03FF /* Target address */
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/*
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* TAR_DATA_CMD - Data Buffer and Command Register 22.2.3
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*
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* RESTART - RW This bit controls whether a forced RESTART is
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* issued before the byte is sent or received.
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*
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* 0 If not set a RESTART is only issued if the transfer
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* direction is changing from the previous command.
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*
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* 1 A RESTART is issued before the byte is sent or
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* received, regardless of whether or not the transfer
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* direction is changing from the previous command.
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*
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* STOP - RW This bit controls whether a STOP is issued after
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* the byte is sent or received.
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*
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* 0 STOP is not issued after this byte, regardless
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* of whether or not the Tx FIFO is empty.
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*
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* 1 STOP is issued after this byte, regardless of
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* whether or not the Tx FIFO is empty. If the
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* Tx FIFO is not empty the master immediately tries
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* to start a new transfer by issuing a START and
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* arbitrating for the bus.
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*
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* i.e. the STOP is issued along with this byte,
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* within the write stream.
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*
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* COMMAND - RW Control whether a read or write is performed.
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*
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* 0 WRITE
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*
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* 1 READ
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*
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* DATA (7:0) - RW Contains the data to be transmitted or received
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* on the I2C bus.
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*
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* NOTE: Writing to this register causes a START + slave + RW to be
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* issued if the direction has changed or the last data byte was
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* sent with a STOP.
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*
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* NOTE: We control termination? so this register must be written
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* for each byte we wish to receive. We can then drain the
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* receive FIFO.
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*/
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#define IG4_DATA_RESTART 0x0400 /* Force RESTART */
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#define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */
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#define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */
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#define IG4_DATA_MASK 0x00FF
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/*
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* SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4
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* SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5
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* FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6
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* FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7
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*
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* COUNT (15:0) - Set the period count to a value between 6 and
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* 65525.
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*/
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#define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */
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/*
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* INTR_STAT - (RO) Interrupt Status Register 22.2.8
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* INTR_MASK - (RW) Interrupt Mask Register 22.2.9
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* RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10
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*
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* GEN_CALL Set only when a general call (broadcast) address
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* is received and acknowleged, stays set until
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* cleared by reading CLR_GEN_CALL.
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*
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* START_DET Set when a START or RESTART condition has occurred
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* on the interface.
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*
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* STOP_DET Set when a STOP condition has occurred on the
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* interface.
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*
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* ACTIVITY Set by any activity on the interface. Cleared
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* by reading CLR_ACTIVITY or CLR_INTR.
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*
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* TX_ABRT Indicates the controller as a transmitter is
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* unable to complete the intended action. When set,
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* the controller will hold the TX FIFO in a reset
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* state (flushed) until CLR_TX_ABORT is read to
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* clear the condition. Once cleared, the TX FIFO
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* will be available again.
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*
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* TX_EMPTY Indicates that the transmitter is at or below
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* the specified TX_TL threshold. Automatically
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* cleared by HW when the buffer level goes above
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* the threshold.
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*
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* TX_OVER Indicates that the processor attempted to write
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* to the TX FIFO while the TX FIFO was full. Cleared
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* by reading CLR_TX_OVER.
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*
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* RX_FULL Indicates that the receive FIFO has reached or
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* exceeded the specified RX_TL threshold. Cleared
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* by HW when the cpu drains the FIFO to below the
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* threshold.
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*
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* RX_OVER Indicates that the receive FIFO was unable to
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* accept new data and data was lost. Cleared by
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* reading CLR_RX_OVER.
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*
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* RX_UNDER Indicates that the cpu attempted to read data
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* from the receive buffer while the RX FIFO was
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* empty. Cleared by reading CLR_RX_UNDER.
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*
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* NOTES ON RAW_INTR_STAT:
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*
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* This register can be used to monitor the GEN_CALL, START_DET,
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* STOP_DET, ACTIVITY, TX_ABRT, TX_EMPTY, TX_OVER, RX_FULL, RX_OVER,
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* and RX_UNDER bits. The documentation is a bit unclear but presumably
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* this is the unlatched version.
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*
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* Code should test FIFO conditions using the I2C_STA (status) register,
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* not the interrupt status registers.
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*/
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#define IG4_INTR_GEN_CALL 0x0800
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#define IG4_INTR_START_DET 0x0400
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#define IG4_INTR_STOP_DET 0x0200
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#define IG4_INTR_ACTIVITY 0x0100
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#define IG4_INTR_TX_ABRT 0x0040
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#define IG4_INTR_TX_EMPTY 0x0010
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#define IG4_INTR_TX_OVER 0x0008
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#define IG4_INTR_RX_FULL 0x0004
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#define IG4_INTR_RX_OVER 0x0002
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#define IG4_INTR_RX_UNDER 0x0001
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#define IG4_INTR_ERR_MASK (IG4_INTR_TX_ABRT | IG4_INTR_TX_OVER | \
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IG4_INTR_RX_OVER | IG4_INTR_RX_UNDER)
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/*
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* RX_TL - (RW) Receive FIFO Threshold Register 22.2.11
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* TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12
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*
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* Specify the receive and transmit FIFO threshold register. The
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* FIFOs have 16 elements. The valid range is 0-15. Setting a
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* value greater than 15 causes the actual value to be the maximum
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* depth of the FIFO.
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*
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* Generally speaking since everything is messaged, we can use a
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* mid-level setting for both parameters and (e.g.) fully drain the
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* receive FIFO on the STOP_DET condition to handle loose ends.
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*/
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#define IG4_FIFO_MASK 0x00FF
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#define IG4_FIFO_LIMIT 16
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/*
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* CLR_INTR - (RO) Clear Interrupt Register 22.2.13
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* CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14
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* CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15
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* CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16
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* CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17
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* CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18
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* CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19
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* CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20
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* CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21
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*
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* CLR_* specific operations clear the appropriate bit in the
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* RAW_INTR_STAT register. Intel does not really document whether
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* these operations clear the normal interrupt status register.
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*
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* CLR_INTR clears bits in the normal interrupt status register and
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* presumably also the raw(?) register? Intel is again unclear.
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*
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* NOTE: CLR_INTR only clears software-clearable interrupts. Hardware
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* clearable interrupts are controlled entirely by the hardware.
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* CLR_INTR also clears the TX_ABRT_SOURCE register.
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*
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* NOTE: CLR_TX_ABORT also clears the TX_ABRT_SOURCE register and releases
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* the TX FIFO from its flushed/reset state, allowing more writes
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* to the TX FIFO.
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*
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* NOTE: CLR_ACTIVITY has no effect if the I2C bus is still active.
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* Intel documents that the bit is automatically cleared when
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* there is no further activity on the bus.
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*/
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#define IG4_CLR_BIT 0x0001 /* Reflects source */
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/*
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* I2C_EN - (RW) I2C Enable Register 22.2.22
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*
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* ABORT Software can abort an I2C transfer by setting this
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* bit. In response, the controller issues the STOP
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* condition over the I2C bus, followed by TX FIFO flush.
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* Hardware will clear the bit once the STOP has
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* been detected. This bit can only be set while the
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* I2C interface is enabled.
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*
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* I2C_ENABLE Enable the controller, else disable it.
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* (Use I2C_ENABLE_STATUS to poll enable status
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* & wait for changes)
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*/
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#define IG4_I2C_ABORT 0x0002
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#define IG4_I2C_ENABLE 0x0001
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/*
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* I2C_STA - (RO) I2C Status Register 22.2.23
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*/
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#define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */
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#define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */
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#define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */
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#define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */
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#define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */
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#define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */
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/*
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* TXFLR - (RO) Transmit FIFO Level Register 22.2.24
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* RXFLR - (RO) Receive FIFO Level Register 22.2.25
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*
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* Read the number of entries currently in the Transmit or Receive
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* FIFOs. Note that for some reason the mask is 9 bits instead of
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* the 8 bits the fill level controls.
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*/
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#define IG4_FIFOLVL_MASK 0x01FF
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/*
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* SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26
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*
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* Set the SDA hold time length register in I2C clocks.
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*/
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#define IG4_SDA_TX_HOLD_MASK 0x0000FFFF
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/*
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* TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27
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*
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* Indicates the cause of a transmit abort. This can indicate a
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* software programming error or a device expected address width
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* mismatch or other issues. The NORESTART conditions and GENCALL_NOACK
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* can only occur if a programming error was made in the driver software.
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*
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* In particular, it should be possible to detect whether any devices
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* are on the bus by observing the GENCALL_READ status, and it might
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* be possible to detect ADDR7 vs ADDR10 mismatches.
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*/
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#define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */
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#define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */
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#define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */
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#define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */
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#define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */
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#define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */
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#define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */
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#define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */
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#define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */
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#define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */
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#define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */
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/*
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* SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28
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*
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* When the controller is a receiver a NACK can be generated on
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* receipt of data.
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*
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* NACK_GENERATE Set to 0 for normal NACK/ACK generation.
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* Set to 1 to generate a NACK after next data
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* byte received.
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*
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*/
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#define IG4_NACK_GENERATE 0x0001
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/*
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* DMA_CTRL - (RW) DMA Control Register 22.2.29
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*
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* Enables DMA on the transmit and/or receive DMA channel.
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*/
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#define IG4_TX_DMA_ENABLE 0x0002
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#define IG4_RX_DMA_ENABLE 0x0001
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/*
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* DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30
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* DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31
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*
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* Similar to RX_TL and TX_TL but controls when a DMA burst occurs
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* to empty or fill the FIFOs. Use the same IG4_FIFO_MASK and
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* IG4_FIFO_LIMIT defines for RX_RL and TX_TL.
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*/
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/* empty */
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/*
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* SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32
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*
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* Set the SDA setup time length register in I2C clocks.
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* The register must be programmed with a value >=2.
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* (Defaults to 0x64).
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*/
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#define IG4_SDA_SETUP_MASK 0x00FF
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/*
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* ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33
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*
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* Control whether the controller responds with a ACK or NACK when
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* it receives an I2C General Call address.
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*
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* If set to 0 a NACK is generated and a General Call interrupt is
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* NOT generated. Otherwise an ACK + interrupt is generated.
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*/
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#define IG4_ACKGC_ACK 0x0001
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/*
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* ENABLE_STATUS - (RO) Enable Status Registger 22.2.34
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*
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* DATA_LOST - Indicates that a slave receiver operation has
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* been aborted with at least one data byte received
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* from a transfer due to the I2C controller being
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* disabled (IG4_I2C_ENABLE -> 0)
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*
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* ENABLED - Intel documentation is lacking but I assume this
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* is a reflection of the IG4_I2C_ENABLE bit in the
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* I2C_EN register.
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*
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*/
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#define IG4_ENASTAT_DATA_LOST 0x0004
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#define IG4_ENASTAT_ENABLED 0x0001
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/*
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* COMP_PARAM1 - (RO) Component Parameter Register 22.2.35
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* Default Value 0x00FFFF6E
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*
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* VALID - Intel documentation is unclear but I believe this
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* must be read as a 1 to indicate that the rest of
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* the bits in the register are valid.
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*
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* HASDMA - Indicates that the chip is DMA-capable. Presumably
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* in certain virtualization cases the chip might be
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* set to not be DMA-capable.
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*
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* INTR_IO - Indicates that all interrupts are combined to
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* generate one interrupt. If not set, interrupts
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* are individual (more virtualization stuff?)
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*
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* HCCNT_RO - Indicates that the clock timing registers are
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* RW. If not set, the registers are RO.
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* (more virtualization stuff).
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*
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* MAXSPEED - Indicates the maximum speed supported.
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*
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* DATAW - Indicates the internal bus width in bits.
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*/
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#define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1)
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#define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1)
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#define IG4_PARAM1_CONFIG_VALID 0x00000080
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#define IG4_PARAM1_CONFIG_HASDMA 0x00000040
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#define IG4_PARAM1_CONFIG_INTR_IO 0x00000020
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#define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010
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#define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C
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#define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003
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#define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000
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#define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004
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#define IG4_CONFIG_MAXSPEED_FAST 0x00000008
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#define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C
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#define IG4_CONFIG_DATAW_8 0x00000000
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#define IG4_CONFIG_DATAW_16 0x00000001
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#define IG4_CONFIG_DATAW_32 0x00000002
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#define IG4_CONFIG_DATAW_RESERVED11 0x00000003
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/*
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* COMP_VER - (RO) Component Version Register 22.2.36
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*
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* Contains the chip version number. All 32 bits.
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*/
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#define IG4_COMP_MIN_VER 0x3131352A
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/*
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* COMP_TYPE - (RO) (linux) Endian and bus width probe
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*
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* Read32 from this register and test against IG4_COMP_TYPE
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* to determine the bus width. e.g. 01404457 = endian-reversed,
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* and 00000140 or 00004457 means internal 16-bit bus (?).
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*
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* This register is not in the intel documentation, I pulled it
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* from the linux driver i2c-designware-core.c.
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*/
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#define IG4_COMP_TYPE 0x44570140
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/*
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* RESETS - (RW) Resets Register 22.2.37
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*
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* Used to reset the I2C host controller by SW. There is no timing
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* requirement, software can assert and de-assert in back-to-back
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* transactions.
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*
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* 00 I2C host controller is NOT in reset.
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* 01 (reserved)
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* 10 (reserved)
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* 11 I2C host controller is in reset.
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*/
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#define IG4_RESETS_ASSERT_HSW 0x0003
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#define IG4_RESETS_DEASSERT_HSW 0x0000
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/* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */
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#define IG4_RESETS_DEASSERT_SKL 0x0003
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#define IG4_RESETS_ASSERT_SKL 0x0000
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/* Newer versions of the I2C controller allow to check whether
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* the above ASSERT/DEASSERT is necessary by querying the DEVIDLE_CONTROL
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* register.
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*
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* the RESTORE_REQUIRED bit can be cleared by writing 1
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* the DEVICE_IDLE status can be set to put the controller in an idle state
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*
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*/
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#define IG4_RESTORE_REQUIRED 0x0008
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#define IG4_DEVICE_IDLE 0x0004
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/*
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* GENERAL - (RW) General Reigster 22.2.38
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*
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* IOVOLT 0=1.8V 1=3.3V
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*
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* LTR 0=Auto 1=SW
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*
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* In Auto mode the BIOS will write to the host controller's
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* AUTO LTR Value register (offset 0x0814) with the active
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* state LTR value, and will write to the SW LTR Value register
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* (offset 0x0810) with the idle state LTR value.
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*
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* In SW mode the SW will write to the host controller SW LTR
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* value (offset 0x0810). It is the SW responsibility to update
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* the LTR with the appropriate value.
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*/
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#define IG4_GENERAL_IOVOLT3_3 0x0008
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#define IG4_GENERAL_SWMODE 0x0004
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/*
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* SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39
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* AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40
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*
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* Default value is 0x00000800 which means the best possible
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* service/response time.
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*
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* It isn't quite clear how the snooping works. There are two scale
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* bits for both sets but two of the four codes are reserved. The
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* *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it
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* indicates that the device cannot tolerate any delay and needs the
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* best possible service/response time.
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*
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* I think this is for snooping (testing) the I2C bus. The lowest
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* delay (0) probably runs the controller polling at a high, power hungry
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* rate. But I dunno.
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*/
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#define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */
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#define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */
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#define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */
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#define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */
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#define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F)
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#define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16)
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#define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */
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#define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */
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#define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */
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#define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */
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#define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F)
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#define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F)
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#endif /* _ICHIIC_IG4_REG_H_ */
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