mirror of
https://github.com/freebsd/freebsd-src
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440e7cb4ac
Reviewed by: jkoshy MFC after: 3 days Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D41271
207 lines
5.9 KiB
C
207 lines
5.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2008 Joseph Koshy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DEV_HWPMC_CORE_H_
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#define _DEV_HWPMC_CORE_H_ 1
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#define IA32_PERF_CAPABILITIES 0x345
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#define PERFCAP_LBR_FORMAT 0x003f
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#define PERFCAP_PEBS_TRAP 0x0040
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#define PERFCAP_PEBS_SAVEARCH 0x0080
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#define PERFCAP_PEBS_RECFORMAT 0x0f00
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#define PERFCAP_SMM_FREEZE 0x1000
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#define PERFCAP_FW_WRITE 0x2000 /* full width write aliases */
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#define IAF_OS 0x1
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#define IAF_USR 0x2
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#define IAF_ANY 0x4
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#define IAF_PMI 0x8
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/*
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* Programmable PMCs.
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*/
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struct pmc_md_iap_op_pmcallocate {
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uint64_t pm_iap_config;
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uint64_t pm_iap_rsp;
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};
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#define IAP_EVSEL(C) ((C) & 0xFF)
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#define IAP_UMASK(C) (((C) & 0xFF) << 8)
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#define IAP_USR (1 << 16)
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#define IAP_OS (1 << 17)
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#define IAP_EDGE (1 << 18)
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#define IAP_INT (1 << 20)
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#define IAP_ANY (1 << 21)
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#define IAP_EN (1 << 22)
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#define IAP_INV (1 << 23)
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#define IAP_CMASK(C) (((C) & 0xFF) << 24)
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#define IAP_EVSEL_GET(C) ((C) & 0xFF)
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#define IAP_UMASK_GET(C) (((C) & 0xFF00) >> 8)
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#define IA_OFFCORE_RSP_MASK_I7WM 0x000000F7FF
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#define IA_OFFCORE_RSP_MASK_SBIB 0x3F807F8FFF
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#ifdef _KERNEL
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/*
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* Fixed-function counters.
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*/
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#define IAF_MASK 0x000000010000000f
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#define IAF_CTR0 0x309
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#define IAF_CTR1 0x30A
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#define IAF_CTR2 0x30B
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/*
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* The IAF_CTRL MSR is laid out in the following way.
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*
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* Bit Position Use
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* 63 - 45 Reserved (do not touch)
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* 44 Ctr 3 Adaptive Record (v5)
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* 43 - 41 Reserved (do not touch)
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* 40 Ctr 2 Adaptive Record (v5)
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* 39 - 37 Reserved (do not touch)
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* 36 Ctr 1 Adaptive Record (v5)
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* 35 - 33 Reserved (do not touch)
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* 32 Ctr 0 Adaptive Record (v5)
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* 15 Ctr 3 PMI
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* 14 Ctr 3 Any Thread (v3)
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* 13-12 Ctr 3 Enable
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* 11 Ctr 2 PMI
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* 10 Ctr 2 Any Thread (v3)
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* 9-8 Ctr 2 Enable
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* 7 Ctr 1 PMI
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* 6 Ctr 1 Any Thread (v3)
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* 5-4 Ctr 1 Enable
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* 3 Ctr 0 PMI
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* 2 Ctr 0 Any Thread (v3)
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* 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable)
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*/
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#define IAF_OFFSET 32
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#define IAF_CTRL 0x38D
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/*
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* Programmable counters.
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*/
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#define IAP_PMC0 0x0C1
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#define IAP_A_PMC0 0x4C1
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/*
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* IAP_EVSEL(n) is laid out in the following way.
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*
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* Bit Position Use
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* 63-35 Reserved (do not touch)
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* 34 Adaptive Record (v5)
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* 33 IN_TX (v3)
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* 32 IN_TXCP (v3)
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* 31-24 Counter Mask
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* 23 Invert
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* 22 Enable
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* 21 Any Thread (v3)
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* 20 APIC Interrupt Enable
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* 19 Pin Control
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* 18 Edge Detect
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* 17 OS
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* 16 User
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* 15-8 Unit Mask
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* 7-0 Event Select
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*/
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#define IAP_EVSEL0 0x186
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/*
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* Simplified programming interface in Intel Performance Architecture
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* v2 and later.
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*/
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#define IA_GLOBAL_STATUS 0x38E
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#define IA_GLOBAL_CTRL 0x38F
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/*
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* IA_GLOBAL_CTRL is laid out in the following way.
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*
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* Bit Position Use
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* 63-49 Reserved (do not touch)
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* 48 Perf Metrics Enable (v5)
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* 47-36 Reserved (do not touch)
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* 35 IAF Counter 3 Enable
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* 34 IAF Counter 2 Enable
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* 33 IAF Counter 1 Enable
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* 32 IAF Counter 0 Enable
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* 31-0 Depends on programmable counters
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*/
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#define IA_GLOBAL_OVF_CTRL 0x390
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#define IA_GLOBAL_STATUS_RESET 0x390
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#define IA_GLOBAL_STATUS_SET 0x391 /* v4 */
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#define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63)
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#define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62)
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#define IA_GLOBAL_STATUS_FLAG_OVFUNCORE (1ULL << 61) /* v3 */
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#define IA_GLOBAL_STATUS_FLAG_ASCI (1ULL << 60) /* v4 */
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#define IA_GLOBAL_STATUS_FLAG_CTR_FRZ (1ULL << 59) /* v4 */
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#define IA_GLOBAL_STATUS_FLAG_LBP_FRZ (1ULL << 58) /* v4 */
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#define IA_GLOBAL_STATUS_FLAG_TRACETOPAPMI (1ULL << 55) /* v4 */
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#define IA_GLOBAL_INUSE 0x392 /* v4 */
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/*
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* Offcore response configuration.
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*/
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#define IA_OFFCORE_RSP0 0x1A6
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#define IA_OFFCORE_RSP1 0x1A7
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struct pmc_md_iaf_pmc {
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uint64_t pm_iaf_ctrl;
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};
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struct pmc_md_iap_pmc {
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uint64_t pm_iap_evsel;
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uint64_t pm_iap_rsp;
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};
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/*
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* Prototypes.
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*/
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int pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu,
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int _version_override);
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void pmc_core_finalize(struct pmc_mdep *_md);
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int pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width);
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int pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width,
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int _flags);
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#endif /* _KERNEL */
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#endif /* _DEV_HWPMC_CORE_H */
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