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4d846d260e
The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch up to that fact and revert to their recommended match of BSD-2-Clause. Discussed with: pfg MFC After: 3 days Sponsored by: Netflix
296 lines
13 KiB
C
296 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: eqos_reg.h 921 2022-08-09 18:38:11Z sos $
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*/
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/*
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* DesignWare Ethernet Quality-of-Service controller
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*/
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#ifndef _EQOS_REG_H
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#define _EQOS_REG_H
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#define GMAC_MAC_CONFIGURATION 0x0000
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#define GMAC_MAC_CONFIGURATION_CST (1U << 21)
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#define GMAC_MAC_CONFIGURATION_ACS (1U << 20)
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#define GMAC_MAC_CONFIGURATION_BE (1U << 18)
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#define GMAC_MAC_CONFIGURATION_JD (1U << 17)
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#define GMAC_MAC_CONFIGURATION_JE (1U << 16)
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#define GMAC_MAC_CONFIGURATION_PS (1U << 15)
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#define GMAC_MAC_CONFIGURATION_FES (1U << 14)
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#define GMAC_MAC_CONFIGURATION_DM (1U << 13)
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#define GMAC_MAC_CONFIGURATION_DCRS (1U << 9)
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#define GMAC_MAC_CONFIGURATION_TE (1U << 1)
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#define GMAC_MAC_CONFIGURATION_RE (1U << 0)
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#define GMAC_MAC_EXT_CONFIGURATION 0x0004
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#define GMAC_MAC_PACKET_FILTER 0x0008
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#define GMAC_MAC_PACKET_FILTER_HPF (1U << 10)
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#define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6)
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#define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6)
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#define GMAC_MAC_PACKET_FILTER_DBF (1U << 5)
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#define GMAC_MAC_PACKET_FILTER_PM (1U << 4)
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#define GMAC_MAC_PACKET_FILTER_HMC (1U << 2)
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#define GMAC_MAC_PACKET_FILTER_HUC (1U << 1)
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#define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
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#define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
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#define GMAC_MAC_HASH_TABLE_REG0 0x0010
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#define GMAC_MAC_HASH_TABLE_REG1 0x0014
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#define GMAC_MAC_VLAN_TAG 0x0050
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#define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1U << 1)
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#define GMAC_MAC_RX_FLOW_CTRL 0x0090
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#define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0)
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#define GMAC_RXQ_CTRL0 0x00A0
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#define GMAC_RXQ_CTRL0_EN_MASK 0x3
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#define GMAC_RXQ_CTRL0_EN_DCB 0x2
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#define GMAC_RXQ_CTRL1 0x00A4
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#define GMAC_MAC_INTERRUPT_STATUS 0x00B0
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#define GMAC_MAC_INTERRUPT_ENABLE 0x00B4
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#define GMAC_MAC_RX_TX_STATUS 0x00B8
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#define GMAC_MAC_RX_TX_STATUS_RWT (1U << 8)
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#define GMAC_MAC_RX_TX_STATUS_EXCOL (1U << 5)
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#define GMAC_MAC_RX_TX_STATUS_LCOL (1U << 4)
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#define GMAC_MAC_RX_TX_STATUS_EXDEF (1U << 3)
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#define GMAC_MAC_RX_TX_STATUS_LCARR (1U << 2)
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#define GMAC_MAC_RX_TX_STATUS_NCARR (1U << 1)
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#define GMAC_MAC_RX_TX_STATUS_TJT (1U << 0)
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#define GMAC_MAC_PMT_CONTROL_STATUS 0x00C0
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#define GMAC_MAC_RWK_PACKET_FILTER 0x00C4
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#define GMAC_MAC_LPI_CONTROL_STATUS 0x00D0
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#define GMAC_MAC_LPI_TIMERS_CONTROL 0x00D4
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#define GMAC_MAC_LPI_ENTRY_TIMER 0x00D8
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#define GMAC_MAC_1US_TIC_COUNTER 0x00DC
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#define GMAC_MAC_PHYIF_CONTROL_STATUS 0x00F8
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#define GMAC_MAC_VERSION 0x0110
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#define GMAC_MAC_VERSION_USERVER_SHIFT 8
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#define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT)
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#define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU
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#define GMAC_MAC_DEBUG 0x0114
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#define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n))
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#define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14
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#define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
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#define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS 0x0200
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#define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21
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#define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16
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#define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8
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#define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_20_35 (2U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_35_60 (3U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_150_250 (4U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_250_300 (5U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_300_500 (6U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_CR_500_800 (7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_SKAP (1U << 4)
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#define GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT 2
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#define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
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#define GMAC_MAC_MDIO_ADDRESS_C45E (1U << 1)
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#define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0)
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#define GMAC_MAC_MDIO_DATA 0x0204
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#define GMAC_MAC_CSR_SW_CTRL 0x0230
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#define GMAC_MAC_ADDRESS0_HIGH 0x0300
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#define GMAC_MAC_ADDRESS0_LOW 0x0304
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#define GMAC_MMC_CONTROL 0x0700
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#define GMAC_MMC_CONTROL_UCDBC (1U << 8)
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#define GMAC_MMC_CONTROL_CNTPRSTLVL (1U << 5)
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#define GMAC_MMC_CONTROL_CNTPRST (1U << 4)
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#define GMAC_MMC_CONTROL_CNTFREEZ (1U << 3)
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#define GMAC_MMC_CONTROL_RSTONRD (1U << 2)
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#define GMAC_MMC_CONTROL_CNTSTOPRO (1U << 1)
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#define GMAC_MMC_CONTROL_CNTRST (1U << 0)
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#define GMAC_MMC_RX_INTERRUPT 0x0704
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#define GMAC_MMC_TX_INTERRUPT 0x0708
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#define GMAC_MMC_RX_INTERRUPT_MASK 0x070C
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#define GMAC_MMC_TX_INTERRUPT_MASK 0x0710
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#define GMAC_TX_OCTET_COUNT_GOOD_BAD 0x0714
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#define GMAC_TX_PACKET_COUNT_GOOD_BAD 0x0718
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#define GMAC_TX_UNDERFLOW_ERROR_PACKETS 0x0748
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#define GMAC_TX_CARRIER_ERROR_PACKETS 0x0760
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#define GMAC_TX_OCTET_COUNT_GOOD 0x0764
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#define GMAC_TX_PACKET_COUNT_GOOD 0x0768
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#define GMAC_RX_PACKETS_COUNT_GOOD_BAD 0x0780
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#define GMAC_RX_OCTET_COUNT_GOOD_BAD 0x0784
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#define GMAC_RX_OCTET_COUNT_GOOD 0x0788
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#define GMAC_RX_MULTICAST_PACKETS_GOOD 0x0790
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#define GMAC_RX_CRC_ERROR_PACKETS 0x0794
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#define GMAC_RX_LENGTH_ERROR_PACKETS 0x07C8
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#define GMAC_RX_FIFO_OVERFLOW_PACKETS 0x07D4
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#define GMAC_MMC_IPC_RX_INTERRUPT_MASK 0x0800
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#define GMAC_MMC_IPC_RX_INTERRUPT 0x0808
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#define GMAC_RXIPV4_GOOD_PACKETS 0x0810
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#define GMAC_RXIPV4_HEADER_ERROR_PACKETS 0x0814
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#define GMAC_RXIPV6_GOOD_PACKETS 0x0824
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#define GMAC_RXIPV6_HEADER_ERROR_PACKETS 0x0828
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#define GMAC_RXUDP_ERROR_PACKETS 0x0834
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#define GMAC_RXTCP_ERROR_PACKETS 0x083C
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#define GMAC_RXICMP_ERROR_PACKETS 0x0844
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#define GMAC_RXIPV4_HEADER_ERROR_OCTETS 0x0854
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#define GMAC_RXIPV6_HEADER_ERROR_OCTETS 0x0868
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#define GMAC_RXUDP_ERROR_OCTETS 0x0874
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#define GMAC_RXTCP_ERROR_OCTETS 0x087C
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#define GMAC_RXICMP_ERROR_OCTETS 0x0884
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#define GMAC_MAC_TIMESTAMP_CONTROL 0x0B00
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#define GMAC_MAC_SUB_SECOND_INCREMENT 0x0B04
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#define GMAC_MAC_SYSTEM_TIME_SECS 0x0B08
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#define GMAC_MAC_SYSTEM_TIME_NS 0x0B0C
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#define GMAC_MAC_SYS_TIME_SECS_UPDATE 0x0B10
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#define GMAC_MAC_SYS_TIME_NS_UPDATE 0x0B14
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#define GMAC_MAC_TIMESTAMP_ADDEND 0x0B18
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#define GMAC_MAC_TIMESTAMP_STATUS 0x0B20
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#define GMAC_MAC_TX_TS_STATUS_NS 0x0B30
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#define GMAC_MAC_TX_TS_STATUS_SECS 0x0B34
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#define GMAC_MAC_AUXILIARY_CONTROL 0x0B40
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#define GMAC_MAC_AUXILIARY_TS_NS 0x0B48
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#define GMAC_MAC_AUXILIARY_TS_SECS 0x0B4C
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#define GMAC_MAC_TS_INGRESS_CORR_NS 0x0B58
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#define GMAC_MAC_TS_EGRESS_CORR_NS 0x0B5C
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#define GMAC_MAC_TS_INGRESS_LATENCY 0x0B68
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#define GMAC_MAC_TS_EGRESS_LATENCY 0x0B6C
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#define GMAC_MAC_PPS_CONTROL 0x0B70
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#define GMAC_MTL_DBG_CTL 0x0C08
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#define GMAC_MTL_DBG_STS 0x0C0C
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#define GMAC_MTL_FIFO_DEBUG_DATA 0x0C10
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#define GMAC_MTL_INTERRUPT_STATUS 0x0C20
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#define GMAC_MTL_INTERRUPT_STATUS_DBGIS (1U << 17)
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#define GMAC_MTL_INTERRUPT_STATUS_Q0IS (1U << 0)
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#define GMAC_MTL_TXQ0_OPERATION_MODE 0x0D00
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
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#define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1)
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#define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0)
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#define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04
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#define GMAC_MTL_TXQ0_DEBUG 0x0D08
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8)
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#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0)
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#define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30
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#define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4)
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#define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3)
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#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34
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#define GMAC_MTL_RXQ0_DEBUG 0x0D38
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#define GMAC_DMA_MODE 0x1000
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#define GMAC_DMA_MODE_SWR (1U << 0)
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#define GMAC_DMA_SYSBUS_MODE 0x1004
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#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24
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#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)
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#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
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#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)
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#define GMAC_DMA_SYSBUS_MODE_MB (1U << 14)
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#define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11)
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#define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3)
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#define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2)
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#define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1)
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#define GMAC_DMA_SYSBUS_MODE_FB (1U << 0)
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#define GMAC_DMA_INTERRUPT_STATUS 0x1008
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#define GMAC_DMA_DEBUG_STATUS0 0x100C
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#define GMAC_AXI_LPI_ENTRY_INTERVAL 0x1040
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#define GMAC_RWK_FILTERn_BYTE_MASK(n) (0x10C0 + 0x4 * (n))
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#define GMAC_RWK_FILTER01_CRC 0x10D0
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#define GMAC_RWK_FILTER23_CRC 0x10D4
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#define GMAC_RWK_FILTER_OFFSET 0x10D8
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#define GMAC_RWK_FILTER_COMMAND 0x10DC
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#define GMAC_DMA_CHAN0_CONTROL 0x1100
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#define GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT 18
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#define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT)
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#define GMAC_DMA_CHAN0_CONTROL_PBLX8 (1U << 16)
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#define GMAC_DMA_CHAN0_TX_CONTROL 0x1104
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#define GMAC_DMA_CHAN0_TX_CONTROL_OSP (1U << 4)
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#define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0)
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#define GMAC_DMA_CHAN0_RX_CONTROL 0x1108
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#define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT 1
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#define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK (0x3FFFU << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT)
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#define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0)
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#define GMAC_DMA_CHAN0_TX_BASE_ADDR_HI 0x1110
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#define GMAC_DMA_CHAN0_TX_BASE_ADDR 0x1114
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#define GMAC_DMA_CHAN0_RX_BASE_ADDR_HI 0x1118
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#define GMAC_DMA_CHAN0_RX_BASE_ADDR 0x111C
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#define GMAC_DMA_CHAN0_TX_END_ADDR 0x1120
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#define GMAC_DMA_CHAN0_RX_END_ADDR 0x1128
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#define GMAC_DMA_CHAN0_TX_RING_LEN 0x112C
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#define GMAC_DMA_CHAN0_RX_RING_LEN 0x1130
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#define GMAC_DMA_CHAN0_INTR_ENABLE 0x1134
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#define GMAC_DMA_CHAN0_INTR_ENABLE_NIE (1U << 15)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_AIE (1U << 14)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_CDE (1U << 13)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_FBE (1U << 12)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_ERI (1U << 11)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_ETI (1U << 10)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_RWT (1U << 9)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_RPS (1U << 8)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_RBU (1U << 7)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_RIE (1U << 6)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_TPU (1U << 2)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_TPS (1U << 1)
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#define GMAC_DMA_CHAN0_INTR_ENABLE_TIE (1U << 0)
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#define GMAC_DMA_CHAN0_RX_WATCHDOG 0x1138
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#define GMAC_DMA_CHAN0_SLOT_CTRL_STATUS 0x113C
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#define GMAC_DMA_CHAN0_CUR_TX_DESC 0x1144
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#define GMAC_DMA_CHAN0_CUR_RX_DESC 0x114C
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#define GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR 0x1154
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#define GMAC_DMA_CHAN0_CUR_RX_BUF_ADDR 0x115C
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#define GMAC_DMA_CHAN0_STATUS 0x1160
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#define GMAC_DMA_CHAN0_STATUS_NIS (1U << 15)
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#define GMAC_DMA_CHAN0_STATUS_AIS (1U << 14)
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#define GMAC_DMA_CHAN0_STATUS_CDE (1U << 13)
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#define GMAC_DMA_CHAN0_STATUS_FB (1U << 12)
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#define GMAC_DMA_CHAN0_STATUS_ERI (1U << 11)
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#define GMAC_DMA_CHAN0_STATUS_ETI (1U << 10)
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#define GMAC_DMA_CHAN0_STATUS_RWT (1U << 9)
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#define GMAC_DMA_CHAN0_STATUS_RPS (1U << 8)
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#define GMAC_DMA_CHAN0_STATUS_RBU (1U << 7)
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#define GMAC_DMA_CHAN0_STATUS_RI (1U << 6)
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#define GMAC_DMA_CHAN0_STATUS_TPU (1U << 2)
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#define GMAC_DMA_CHAN0_STATUS_TPS (1U << 1)
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#define GMAC_DMA_CHAN0_STATUS_TI (1U << 0)
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#define EQOS_TDES2_IOC (1U << 31)
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#define EQOS_TDES3_OWN (1U << 31)
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#define EQOS_TDES3_FD (1U << 29)
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#define EQOS_TDES3_LD (1U << 28)
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#define EQOS_TDES3_DE (1U << 23)
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#define EQOS_TDES3_OE (1U << 21)
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#define EQOS_TDES3_ES (1U << 15)
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#define EQOS_RDES3_OWN (1U << 31)
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#define EQOS_RDES3_IOC (1U << 30)
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#define EQOS_RDES3_BUF1V (1U << 24)
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#define EQOS_RDES3_GP (1U << 23)
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#define EQOS_RDES3_OE (1U << 21)
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#define EQOS_RDES3_RE (1U << 20)
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#define EQOS_RDES3_LENGTH_MASK 0x7FFFU
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#endif
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