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Apply the following automated changes to try to eliminate no-longer-needed sys/cdefs.h includes as well as now-empty blank lines in a row. Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/ Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/ Remove /\n+#if.*\n#endif.*\n+/ Remove /^#if.*\n#endif.*\n/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/ Sponsored by: Netflix
153 lines
4.3 KiB
C
153 lines
4.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Alstom Group.
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/enetc/enetc_hw.h>
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#include <dev/enetc/enetc_mdio.h>
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#define ENETC_MDIO_RD4(regs, base, off) \
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bus_read_4((regs), (base) + (off))
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#define ENETC_MDIO_WR4(regs, base, off, value) \
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bus_write_4((regs), (base) + (off), (value))
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static int
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enetc_mdio_wait(struct resource *regs, int mdio_base)
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{
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int i;
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uint32_t val;
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i = 0;
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do {
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DELAY(100);
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val = ENETC_MDIO_RD4(regs, mdio_base, ENETC_MDIO_CFG);
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if ((val & MDIO_CFG_BSY) == 0)
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return (0);
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} while (i++ < ENETC_TIMEOUT);
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return (ETIMEDOUT);
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}
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int
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enetc_mdio_read(struct resource *regs, int mdio_base, int phy, int reg)
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{
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uint32_t mdio_cfg, mdio_ctl;
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uint16_t dev_addr;
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mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
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if (reg & MII_ADDR_C45) {
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/* clause 45 */
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dev_addr = (reg >> 16) & 0x1f;
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mdio_cfg |= MDIO_CFG_ENC45;
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} else {
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/* clause 22 */
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dev_addr = reg & 0x1f;
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mdio_cfg &= ~MDIO_CFG_ENC45;
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}
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CFG, mdio_cfg);
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if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT)
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return (EIO);
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/* Set port and device addr. */
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mdio_ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(dev_addr);
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CTL, mdio_ctl);
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/* Set the register address. */
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if (reg & MII_ADDR_C45) {
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_ADDR, reg & 0xffff);
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if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT)
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return (EIO);
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}
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/* Initiate the read. */
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CTL, mdio_ctl | MDIO_CTL_READ);
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if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT)
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return (EIO);
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/* Check if any error occurred while reading PHY register. */
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if (ENETC_MDIO_RD4(regs, mdio_base, ENETC_MDIO_CFG) & MDIO_CFG_RD_ER)
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return (ENXIO);
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return (MDIO_DATA(ENETC_MDIO_RD4(regs, mdio_base, ENETC_MDIO_DATA)));
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}
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int
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enetc_mdio_write(struct resource *regs, int mdio_base, int phy, int reg,
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int data)
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{
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uint32_t mdio_cfg, mdio_ctl;
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uint16_t dev_addr;
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mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
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if (reg & MII_ADDR_C45) {
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/* clause 45 */
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dev_addr = (reg >> 16) & 0x1f;
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mdio_cfg |= MDIO_CFG_ENC45;
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} else {
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/* clause 22 */
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dev_addr = reg & 0x1f;
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mdio_cfg &= ~MDIO_CFG_ENC45;
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}
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CFG, mdio_cfg);
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if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT)
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return (EIO);
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/* Set port and device addr. */
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mdio_ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(dev_addr);
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CTL, mdio_ctl);
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/* Set the register address. */
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if (reg & MII_ADDR_C45) {
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_ADDR, reg & 0xffff);
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if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT)
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return (EIO);
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}
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/* Write the value. */
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ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_DATA, MDIO_DATA(data));
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if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT)
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return (EIO);
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return (0);
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}
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